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library IEEE, EXEMPLAR; use IEEESTD_LOGIC_1164all; use
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EXEMPLAREXEMPLAR_1164all; -- Library use clause for technology cells library altera ; use alteraall ;
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entity adder is port ( a : IN std_logic_vector (7 DOWNTO 0) ; b : IN std_logic_vector (7 DOWNTO 0) ; c : OUT std_logic_vector (7 DOWNTO 0)) ; end adder ; architecture test of adder is component XOR2 port ( Y : OUT std_logic ; IN1 : IN std_logic ; IN2 : IN std_logic) ; end component ; component LCELL port ( Y : OUT std_logic ; IN1 : IN std_logic) ; end component ; component AND2 port ( Y : OUT std_logic ; IN1 : IN std_logic ; IN2 : IN std_logic) ; end component; signal c_dup0_7, c_dup0_6, c_dup0_5, c_dup0_4, c_dup0_3, c_dup0_2, c_dup0_1, c_dup0_0, modgen_0_l1_l0_c_int_7, modgen_0_l1_l0_c_int_6, modgen_0_l1_l0_c_int_5, modgen_0_l1_l0_c_int_4, modgen_0_l1_l0_c_int_3, modgen_0_l1_l0_c_int_2, modgen_0_l1_l0_c_int_1, modgen_0_l1_l0_l0_0_l0_s1, modgen_0_l1_l0_l0_0_l0_s2, modgen_0_l1_l0_l0_0_l0_w1, modgen_0_l1_l0_l0_0_l0_w2, modgen_0_l1_l0_l0_0_l0_w3, modgen_0_l1_l0_l0_0_l0_w4, b_2_int, b_1_int, b_0_int, U_0: std_logic ; begin modgen_0_l1_l0_l0_0_l0_sum0 : XOR2 port map ( Y=> modgen_0_l1_l0_l0_0_l0_s1, IN1=>a_0_int, IN2=>U_0); modgen_0_l1_l0_l0_0_l0_sum1 : XOR2 port map ( Y=>
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modgen_0_l1_l0_l0_0_l0_s2, IN1=>modgen_0_l1_l0_l0_0_l0_s1, IN2=> b_0_int); modgen_0_l1_l0_l0_0_l0_sum2 : LCELL port map ( Y=>c_dup0_0, IN1=> modgen_0_l1_l0_l0_0_l0_s2); modgen_0_l1_l0_l0_0_l0_c0 : AND2 port map ( Y=>modgen_0_l1_l0_l0_0_l0_w1, IN1=>a_0_int, IN2=>b_0_int); modgen_0_l1_l0_l0_0_l0_c1 : AND2 port map ( Y=>modgen_0_l1_l0_l0_0_l0_w2, IN1=>a_0_int, IN2=>U_0); modgen_0_l1_l0_l0_0_l0_c2 : AND2 port map ( Y=>modgen_0_l1_l0_l0_0_l0_w3, IN1=>U_0, IN2=>b_0_int); ix43 : OUTBUF port map ( \OUT\=>c(3), \IN\=>c_dup0_3); ix44 : OUTBUF port map ( \OUT\=>c(2), \IN\=>c_dup0_2); ix45 : OUTBUF port map ( \OUT\=>c(1), \IN\=>c_dup0_1); ix46 : OUTBUF port map ( \OUT\=>c(0), \IN\=>c_dup0_0); U_0_XMPLR : GND port map ( Y=>U_0); end test ;
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Notice that all of the other interconnect signal names have names such as modgen_0_11_xx or ix123 There is no corresponding signal name in the source file to specify the signal name; therefore, the synthesis tool generates names for these signals The netlist can be used to figure out how well the synthesizer implemented a part of the design, or to track down a problem net It can be very useful to find out why a critical path was implemented too slowly When the netlist meets the designer s timing, area, power, and other constraints, the next step is to pass the netlist to the gate level simulator This simulator checks the functionality of the synthesized design
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Some designers might want to do a quick check on the output of the synthesis tool to make sure that the synthesis tool produced a design that is functionally correct If proper design rules are followed for the input VHDL description, the synthesis tool should never generate an output that is functionally different from the RTL VHDL input, unless the tool has a bug However, if some of the warnings or errors are ignored or some
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part of the design is written using a strange VHDL style, the synthesizer can produce an output netlist that does not exactly match the RTL input in terms of functionality Most designers like to run a quick check on the results of the synthesis tool to make sure the synthesis tool produced a functionally correct output To do this, the designer runs a functional gate-level verification The designer reads the output VHDL netlist from the synthesis tool plus a library of the synthesis primitives into the VHDL simulator and runs the simulation using the RTL verification vectors If the design matches, then the synthesis tool did not produce logic mismatches; if it does not match, the designer needs to debug the VHDL RTL description to see what is wrong The most common method for performing this step is to run a VITAL simulation of the netlist from the synthesis tool For a completely functional simulation, no timing is back-annotated If the synthesis tool supports estimated timing and SDF file generation, the synthesis tool could write the VHDL netlist and an SDF timing file for the design The designer could use these two files to run a VITAL simulation with estimated timing After the design has been functionally verified, it is passed to the place and route tools to implement the design
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