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Decoding QR-Code in Visual C# High-Level Design Flow

High-Level Design Flow
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Static Timing
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For designs of 10,000 gates to 100,000 gates, post route timing simulation can be a good method of verifying design functionality and timing However, as designs get larger, or if the designer does not have test vectors, the designer can use static timing analysis to make sure the design meets the timing requirements A static timing analyzer traces each path in the design and keeps track of the timing from a clock edge or an input A timing report is then generated in a number of formats For instance, the designer can ask for all paths and get an enormous listing of every path in the design A more intelligent method, however, is to ask for the most timing critical paths in the design and make sure the timing constraints have been met Typical static timing analyzers have a number of report types that can be generated so that the designer can make sure the critical paths of the design can be found and verified to be within the required specifications If paths are not within the specifications, the static timing analyzer shows the entire path so that the designer can try to fix the problem
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SUMMARY
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In this chapter, the complete VHDL design process using synthesis was described This process is very similar no matter which VHDL synthesis or simulation tool is used The designer must follow a number of steps that add more detail to the design At each step, the designer has checks to make sure that the correct behavior is being implemented At the beginning of the process, RTL simulation is used to verify correctness After synthesis, the netlist, timing report, and area report are all examined to make sure the design fits the designer s constraints Functional simulation is then run to verify that the synthesis tool produced a functionally correct design The design is put through the place and route process to implement the design in the target technology The final check is then to verify using post route gate level simulation that the design is functionally correct and meets timing
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CHAPTER
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Top-Level System Design
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In the last few chapters, we have discussed VHDL language features and the VHDL synthesis process In the next few chapters, we tie all of these ideas together by developing a top-down design for a small CPU design, verify its functionality, verify that it can be synthesized, and implement the design in an FPGA device
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Figure 12-1 CPU Block Diagram
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OpRegsel Reg0 Reg1 Reg2 Reg3 Reg7 OutReg Outsel ProgCnt Progsel AddrReg Addr(15:0) Data(15:0) Addrsel Ready Regsel Shifter Shiftsel Alusel ALU Compout Comp OpReg
Twelve
Instrsel InstrReg
Compsel
Clock
Reset Control
CPU Design
The example is a small, 16-bit microprocessor A block diagram is shown in Figure 12-1 The processor contains a number of basic pieces There is a register array of eight 16-bit registers, an ALU (Arithmetic Logic Unit), a shifter, a program counter, an instruction register, a comparator, an address register, and a control unit All of these units communicate through a common, 16-bit tristate data bus
Top-Level System Operation
The top-level design consists of the processor block and a memory block communicating through a bidirectional databus, an address bus, and a few control lines The processor fetches instructions from the external memory and executes these instructions to run a program These instructions are
Top-Level System Design
stored in the instruction register and decoded by the control unit The control unit causes the appropriate signal interactions to make the processor unit execute the instruction If the instruction is an add of two registers, the control unit would cause the first register value to be written to register OpReg for temporary storage The second register value would then be placed on the data bus The ALU would be placed in add mode and the result would be stored in register OutReg Register OutReg would store the resulting value until it is copied to the final destination When executing an instruction, a number of steps take place The program counter holds the address in memory of the current instruction After an instruction has finished execution, the program counter is advanced to where the next instruction is located If the processor is executing a linear stream of instructions, this is the next instruction If a branch was taken, the program counter is loaded with the next instruction location directly The control unit copies the program counter value to the address register, which outputs the new address on the address bus At the same time, the control unit sets the R/W (read write signal) to a 0 value for a read operation and sets signal VMA (Valid Memory Address) to a 1 , signaling the memory that the address is now valid The memory decodes the address and places the memory data on the data bus When the data has been placed on the data bus, the memory has set the READY signal to a 1 value indicating that the memory data is ready for consumption The control unit causes the memory data to be written into the instruction register The control unit now has access to the instruction and decodes the instruction The decoded instruction executes, and the process starts over again
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