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Instructions
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Instructions can be divided into a number of different types as follows: I Load These instructions load register values from other registers, memory locations, or with immediate values given in the instruction I Store These instructions store register values to memory locations I Branch These instructions cause the processor to go to another location in the instruction stream Some branch instructions test values before branching; others branch without testing
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Twelve
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I ALU These instructions perform arithmetic and logical operations such as ADD, SUBTRACT, OR, AND, and NOT I Shift These instructions use the shift unit to perform shift operations on the data passed to it
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Sample Instruction Representation
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Instructions share common attributes, but come in a number of flavors Sample instructions are shown in Figure 12-2 All instructions contain the opcode in the five most significant bits of the instruction Single-word instructions also contain two 3-bit register fields in the lowest 6 bits of the instruction Some instructions, such as INC (Increment), only use one of the fields, but other instructions, such as MOV (Move), use both register fields to specify the From register and the To register In double-word instructions, the first word contains the opcode and destination register address, and the second word contains the immediate instruction location or data value to be loaded For instance, a LoadI (Load Immediate) instruction would look like this:
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LoadI 1, 16#15
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Figure 12-2 Instruction Words
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Opcode 15 14 13 12 11 Single Word 5
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DST 1 0
Opcode 15 14 13 12 11 Address or Data 2
DST 1 0
11 Double Word
Top-Level System Design
Opcode DST 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1
Figure 12-3 Instruction Data
1 LoadI
This instruction loads the hex value 15 into register 1 The instruction words look like those shown in Figure 12-3 When the control unit decodes the opcode of the first word, it determines that the instruction is two words long and loads the second word to complete the instruction The instructions implemented in the processor and their opcodes are listed in Figure 12-4 Not all of the possible instructions have been implemented in this processor example to limit the complexity for ease of publication Typical commercial processors are much more complicated and have pipelined instruction streams for faster execution To reduce complexity, this example is not pipelined
CPU Top-Level Design
The next few sections contain the VHDL description for each of the CPU components First of all, a top-level package cpu_libvhd is needed to describe the signal types that are used to communicate between the CPU components Following is this package:
library IEEE; use IEEEstd_logic_1164all; use IEEEstd_logic_arithall; package cpu_lib is type t_shift is (shftpass, shl, shr, rotl, rotr); subtype t_alu is unsigned(3 downto 0); constant alupass : unsigned(3 downto 0) := 0000 ;
Figure 12-4 Opcode Table
OPCODE 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 INSTRUCTION NOP LOAD STORE MOVE LOADI BRANCHI BRANCHGTI INC DEC AND OR XOR NOT ADD SUB ZERO BRANCHLTI BRANCHLT BRANCHNEQ BRANCHNEQI BRANCHGT BRANCH BRANCHEQ BRANCHEQI BRANCHLTEI BRANCHLTE SHL SHR ROTR ROTL NOTE
Twelve
No operation Load register Store register Move value to register Load register with immediate value Branch to immediate address Branch greater than to immediate address Increment Decrement And two registers Or two registers Xor two registers Not a register value Add two registers Subtract two registers Zero a register Branch less than to immediate address Branch less than Branch not equal Branch not equal to immediate address Branch greater than Branch all the time Branch if equal Branch if equal to immediate address Branch if less or equal to immediate address Branch if less or equal Shift left Shift right Rotate right Rotate left
constant constant constant constant constant constant constant constant constant
andOp : unsigned(3 downto 0) := 0001 ; orOp : unsigned(3 downto 0) := 0010 ; notOp : unsigned(3 downto 0) := 0011 ; xorOp : unsigned(3 downto 0) := 0100 ; plus : unsigned(3 downto 0) := 0101 ; alusub : unsigned(3 downto 0) := 0110 ; inc : unsigned(3 downto 0) := 0111 ; dec : unsigned(3 downto 0) := 1000 ; zero : unsigned(3 downto 0) := 1001 ;
type t_comp is (eq, neq, gt, gte, lt, lte); subtype t_reg is std_logic_vector(2 downto 0); type state is (reset1, reset2, reset3, reset4, reset5, type state is (reset6, execute, nop, load, store, move,
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