barcode scanner c# code project Figure 13-4 Comp Interface in Visual C#.NET

Scanner QR Code 2d barcode in Visual C#.NET Figure 13-4 Comp Interface

Figure 13-4 Comp Interface
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sel Comp
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compout
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Figure 13-5 Comp Operation Table
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Sel input value EQ NEQ GT GTE LT LTE
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Comparison Compout = 1 when a equals b Compout = 1 when a is not equal to b Compout = 1 when a is greater than b Compout = 1 when a is greater than or equal to b Compout = 1 when a is less than b Compout = 1 when a is less than or equal to b
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use workcpu_liball; entity comp is port( a, b : in bit16; sel : in t_comp; compout : out std_logic); end comp; architecture rtl of comp is begin compproc: process(a, b, sel) begin case sel is when eq => if a = b then compout <= 1 after else compout <= 0 after end if; when neq => if a /= b then compout <= 1 after else compout <= 0 after end if; when gt => if a > b then compout <= 1 after else compout <= 0 after end if; when gte => if a >= b then compout <= 1 after else compout <= 0 after end if; when lt => if a < b then compout <= 1 after else compout <= 0 after end if; when lte => if a <= b then compout <= 1 after else compout <= 0 after end if; end case; end process; end rtl;
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1 ns; 1 ns;
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1 ns; 1 ns;
1 ns; 1 ns;
1 ns; 1 ns;
1 ns; 1 ns;
CPU: Synthesis Description
The comparator consists of a large case statement where each branch of the case statement contains an IF If the condition tested is true, a 1 value is assigned; otherwise, a 0 is assigned Again, each assignment occurs after 1 nanosecond to remove delta delay problems
Control
The control entity provides the necessary signal interactions to make the data flow properly through the CPU and perform the expected functions Architecture rtl contains a state machine that causes all appropriate signal values to update based on the current state and input signals and produce a next state for the state machine A symbol for the control block is shown in Figure 13-6 The control symbol has only a few inputs, but a lot of outputs The control block provides all of the control signals to regulate data traffic for the CPU Following is the VHDL description for the CPU:
library IEEE; use IEEEstd_logic_1164all; use workcpu_liball; entity control is port( clock : in std_logic; port( reset : in std_logic; port( instrReg : in bit16; port( compout : in std_logic; port( ready : in std_logic; port( progCntrWr : out std_logic; port( progCntrRd : out std_logic; port( addrRegWr : out std_logic; port( addrRegRd : out std_logic; port( outRegWr : out std_logic; port( outRegRd : out std_logic; port( shiftSel : out t_shift; port( aluSel : out t_alu; port( compSel : out t_comp; port( opRegRd : out std_logic; port( opRegWr : out std_logic; port( instrWr : out std_logic; port( regSel : out t_reg; port( regRd : out std_logic; port( regWr : out std_logic; port( rw : out std_logic; port( vma : out std_logic port); end control;
Figure 13-6 Control Symbol
ProgCntrWr Reset Clock InstrReg Compout Ready ProgCntrRd AddrRegWr AddrRegRd OutRegWr OutRegRd ShiftSel AluSel CompSel Control OpRegRd OpRegWr InstrWr RegSel RegRd RegWr Rw Vma
Thirteen
architecture rtl of control is signal current_state, next_state : state; begin nxtstateproc: process( current_state, instrReg, compout, nxtstateproc: process( ready) begin progCntrWr <= 0 ; progCntrRd <= 0 ; addrRegWr <= 0 ; outRegWr <= 0 ; outRegRd <= 0 ; shiftSel <= shftpass; aluSel <= alupass; compSel <= eq; opRegRd <= 0 ; opRegWr <= 0 ; instrWr <= 0 ; regSel <= 000 ; regRd <= 0 ; regWr <= 0 ; rw <= 0 ;
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