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CPU: Synthesis Description
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The reset of the description for the state machine contains the state transitions for the rest of the instructions that have been implemented As mentioned previously, not all of the instructions have been implemented and are left as an exercise for the reader
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The reg entity is used for the address register and the instruction register These registers need to be able to capture the input data on a rising edge of the clk input and drive output q with the captured data The value of input a is assigned to output q when a rising edge occurs on input clk The assignment is delayed by 1 nanosecond to remove delta delay problems during simulation A symbol for the reg entity is shown in Figure 13-7 The reg symbol contains three ports Port a is the data input port, port q is the data output port, and port clk controls when the data is stored in the reg entity Following is the VHDL description for entity reg:
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library IEEE; use IEEEstd_logic_1164all; use workcpu_liball; entity reg is port( a : in bit16; port( clk : in std_logic; port( q : out bit16); end reg; architecture rtl of reg is begin regproc: process begin wait until clk event and clk = 1 ; q <= a after 1 ns; end process; end rtl;
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Figure 13-7 Reg Symbol
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Process regproc is triggered when a rising edge occurs on input clk When the process is triggered, input a is copied to output q
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Regarray
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The regarray entity is used to model the set of registers within the CPU that are used to store intermediate values during instruction processing These registers are read from and written to during the execution of instructions The set of registers is modeled as a RAM of eight 16-bit words The symbol for the regarray entity is shown in Figure 13-8 To write a location in the regarray, set input sel to the location to be written, input data with the data to be written, and put a rising edge on input clk To read a location from regarray, set input sel to the location to be read and set input en to a 1 ; the data is output on port q The register array is modeled as two separate processes as shown in the following:
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library IEEE; use IEEEstd_logic_1164all; use IEEEstd_logic_unsignedall; use workcpu_liball; entity regarray is port( data : in bit16; port( sel : in t_reg; port( en : in std_logic; port( clk : in std_logic; port( q : out bit16); end regarray;
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Figure 13-8 RegArray Symbol
data
RegArray
CPU: Synthesis Description
architecture rtl of regarray is type t_ram is array (0 to 7) of bit16; signal temp_data : bit16; begin process(clk,sel) variable ramdata : t_ram; begin if clk event and clk = 1 then ramdata(conv_integer(sel)) := data; end if; temp_data <= ramdata(conv_integer(sel)) after 1 ns; end process; process(en, temp_data) begin if en = 1 then q <= temp_data after 1 ns; else q <= ZZZZZZZZZZZZZZZZ after 1 ns; end if; end process; end rtl;
The first process models the part of the RAM that stores the data This process contains a local variable ramdata that is used to store the data written to the regarray entity When the clk signal has a rising edge, the location selected by input sel is updated with the new value This process also writes the location to a signal called temp_data to pass the value to the second process The reason for this is that this model was written using VHDL 87, and variables cannot be shared between processes In VHDL 93, sharing variables between processes is legal but has other synthesis ramifications The second process is used to read data from the regarray Whenever input sel changes, the first process updates the value of temp_data Signal temp_data is passed to the second process to pass the memory data The second process outputs the value of temp_data if the en signal is 1 ; otherwise, it puts out Z values The Z values signify that the regarray entity is not driving the output when the en input is unasserted A smart synthesis tool reading this design can realize that the regarray entity can be implemented by a RAM device in the target technology and provide the proper mapping For instance, if the design were to be mapped to an FPGA technology that included RAM in the architecture, the synthesis tool could map the regarray entity to an onboard RAM device Using such an implementation instead of a set of flip-flops and gates creates a smaller and faster implementation
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