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The next device to be described is the shift entity The shift entity is used to perform shifting and rotation operations within the CPU The shift entity has a 16-bit input bus, a 16-bit output bus, and a sel input that determines which shift operation to perform This is shown by the symbol in Figure 13-9 The types of shift operations that can be performed by the shift entity are shown in Figures 13-10 and 13-11 As can be seen by the figures, the shift entity can perform a shift left, shift right, rotate left, and rotate right operation One operation that is not shown by the figures is a pass through operation in which all input bits are passed through to the output unchanged Following is an entity that performs these operations:
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library IEEE; use IEEEstd_logic_1164all; use workcpu_liball; entity shift port ( a : port( sel port( y : end shift; is in bit16; : in t_shift; out bit16);
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architecture rtl of shift is begin shftproc: process(a, sel) begin case sel is when shftpass => y <= a after 1 ns; when shl => y <= a(14 downto 0) & 0 after 1 ns; when shr => y <= 0 & a(15 downto 1) after 1 ns;
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Figure 13-9 Shift Symbol
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CPU: Synthesis Description
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0 0 0 0 0 0 0 0 0 0 1 0 1 0 1
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Figure 13-10 Shift Operations
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Shift Left
Shift Right
when rotl => y <= a(14 downto 0) & a(15) after 1 ns; when rotr => y <= a(0) & a(15 downto 1) after 1 ns; end case; end process; end rtl;
The shftpass mode allows the shifter to pass the input data to the output without any shift operations This mode is quite common because all of the ALU operations flow through the shift entity, and very few instructions are actually performing a shift operation
Figure 13-11 Rotate Operations
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Rotate Left
Rotate Right
The shl and shr selections perform shift left and shift right operations, respectively The rotl and rotr selections perform rotate left and rotate right operations, respectively
Trireg
The last component of the CPU is the tristate register component, trireg The tristate register is connected to the main data bus and can store information from the data bus as well as drive information to the data bus The trireg entity has four ports as shown in Figure 13-12 Input a is the data input to the register, and port q is the data output from the register Input clk is used to store a new value into the register
CPU: Synthesis Description
Figure 13-12 Trireg Symbol
Trireg
When a rising edge is applied to input clk, the data on input a is stored in the register Input en is used to control output q When en is a 1 value, the register state is driven to output q When en is a 0 , output q is a high impedance value and not driving This functionality is implemented by entity trireg shown in the following:
library IEEE; use IEEEstd_logic_1164all; use workcpu_liball; entity trireg is port( a : in bit16; port( en : in std_logic; port( clk : in std_logic; port( q : out bit16); end trireg; architecture rtl of trireg is signal val : bit16; begin triregdata: process begin wait until clk event and clk = 1 ; val <= a; end process; trireg3st: process(en, val) begin if en = 1 then q <= val after 1 ns; elsif en = 0 then q <= ZZZZZZZZZZZZZZZZ after 1 ns; -- exemplar_translate_off else
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q <= XXXXXXXXXXXXXXXX after 1 ns; -- exemplar_translate_on end if; end process; end rtl;
The functionality is described by two processes that use a signal to communicate much like the regarray entity The first process controls when signal val is written Signal val is written only on the rising edge of input clk The second process transfers the value of signal val only when input en is a 1 value; otherwise, a value of Z is output
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