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SUMMARY
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When all of these entities are connected together correctly, the functionality of the CPU results The next two chapters focus on simulating the design for proper operation and synthesizing the design to a target device
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CHAPTER
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CPU: RTL Simulation
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In this chapter, a VHDL simulator is used to verify the functionality of the CPU VHDL RTL description The VHDL RTL description of the CPU is simulated with a standard VHDL simulator to verify that the description is correct A simulator needs two inputs: the description of the design and stimulus to drive the design Sometimes designs are self-stimulating and do not need any external stimulus, but in most cases, VHDL designers use a VHDL testbench of one kind or another to drive the design being tested The structure of the design looks like Figure 14-1 The top-level design description instantiates two components: the first being the design under test (DUT) and the second the stimulus driver These components are connected with signals that represent the external environment of the DUT The top level of the design does not contain any external ports, just internal signals that connect the two instantiated components
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Top Level
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Figure 14-1 Top-Level Design Structure
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Design Under Test
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Testbenches
A testbench is used to verify the functionality of a design The testbench allows the design to verify the functionality of the design at each step in the HDL synthesis-based methodology When the designer makes a small change to fix an error, the change can be tested to make sure that it did not affect other parts of the design New versions of the design can be verified against known good results to verify compatibility A testbench is at the highest level in the hierarchy of the design The testbench instantiates the design under test (DUT) The testbench provides the necessary input stimulus to the DUT and examines the output from the DUT Figure 14-2 shows a block diagram of how this process appears The testbench encapsulates the stimulus driver, known good results, and DUT, and contains internal signals to make the proper connections The stimulus driver drives inputs into the DUT The DUT responds to the input signals and produces output results Finally, a compare function within the testbench compares the results from the DUT against those known good results and reports any discrepancies That is the basic function of a testbench, but there are a number of methods of writing a testbench and each method has advantages and disadvantages
CPU: RTL Simulation
Testbench
Figure 14-2 Testbench Block Diagram
Stimulus Driver
Errors
Good Results
Kinds of Testbenches
There is a myriad of ways to write a testbench, but some of the most common are described in this section The following are the most common testbench types: I Stimulus only Contains only the stimulus driver and DUT; does not contain any results verification I Full testbench Contains stimulus driver, known good results, and results comparison I Simulator specific Testbench is written in a simulator-specific format I Hybrid testbench Combines techniques from more than one testbench style I Fast testbench Testbench written to get ultimate speed from simulation To show the different types of testbenches, a common example is used To make it simple to understand the stimulus and response, a counter example is used The following description is the package, entity, and architecture for an 8-bit counter:
Fourteen
PACKAGE count_types IS SUBTYPE bit8 is INTEGER RANGE 0 to 255; END count_types; LIBRARY IEEE; USE IEEEstd_logic_1164all; USE workcount_typesall; ENTITY count IS PORT (clk : IN std_logic; ld : IN std_logic; up_dwn : IN std_logic; clk_en : IN std_logic; din : IN bit8; qout : INOUT bit8); END count; ARCHITECTURE synthesis OF count IS SIGNAL count_val : bit8; BEGIN PROCESS(ld, up_dwn, din, qout) BEGIN IF ld = 1 THEN count_val <= din; ELSIF up_dwn = 1 THEN IF (qout >= 255) THEN count_val <= 0; ELSE count_val <= count_val + 1; END IF; ELSE IF (qout <= 0) THEN count_val <= 255; ELSE count_val <= count_val - 1; END IF; END IF; END PROCESS; PROCESS BEGIN WAIT UNTIL clk EVENT AND clk = 1 ; IF clk_en = 1 THEN qout <= count_val; END IF; END PROCESS; END synthesis;
Package count_types contains the type declaration for the 8-bit signal type used in the counter The counter is loadable, counts up and down, and contains a clock enable The counter is implemented as two processes: a
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