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combinational process and a sequential process The combinational process calculates the next state of the counter, and the sequential process keeps track of the current state of the counter and updates the next state of the counter on a rising edge of the clk input We use the counter to discuss a number of different types of testbenches
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Stimulus Only
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The stimulus only testbench contains the stimulus driver and DUT blocks of a testbench The verification process is left to the designer This type of testbench is useful at the beginning of a design project when no known good vectors exist, or for a quick check of an entity Following is an example stimulus only testbench:
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ENTITY testbench IS END; ------------------------------------------------------------ STIMULUS ONLY -- testbench for 8-bit loadable counter -- reads from file countertxt ----------------------------------------------------------LIBRARY ieee; USE ieeestd_logic_1164ALL; USE stdtextioALL; USE ieeestd_logic_textioall; USE WORKcount_typesall; ARCHITECTURE stimonly OF testbench IS ------------------------------------ component declaration for counter ----------------------------------COMPONENT count PORT (clk : IN std_logic; ld : IN std_logic; up_dwn : IN std_logic; clk_en : IN std_logic; din : IN bit8; qout : INOUT bit8); END COMPONENT; SIGNAL clk, ld, up_dwn, clk_en : std_logic; SIGNAL qout, din : bit8; BEGIN -- instantiate the component uut: count PORT MAP(clk => clk, ld => ld, up_dwn => up_dwn,
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clk_en => clk_en, din => din, qout => qout);
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-- provide stimulus and check the result test: PROCESS VARIABLE tmpclk, tmpld, tmpup_dwn, tmpclk_en : std_logic; VARIABLE tmpdin : integer; FILE vector_file : text IS IN countertxt ; VARIABLE l : line; VARIABLE vector_time : time; VARIABLE r : real; VARIABLE good_number, good_val : boolean; VARIABLE space : character; BEGIN WHILE NOT endfile(vector_file) LOOP readline(vector_file, l); -- read the time from the beginning of the line -- skip the line if it doesn t start with a number read(l, r, good => good_number); NEXT WHEN NOT good_number; vector_time := r * 1 ns; IF (now < vector_time) THEN WAIT FOR vector_time - now; END IF; read(l, space); --- skip a space -- convert real number to time -- wait until the vector time
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-- read clk value read(l, tmpclk, good_val); assert good_val REPORT bad clk value ; -- read ld value read(l,tmpld, good_val); assert good_val REPORT bad ld value ; -- read up_dwn value read(l,tmpup_dwn, good_val); assert good_val REPORT bad up_dwn value ; -- read clk_en value read(l,tmpclk_en, good_val); assert good_val REPORT bad clk_en value ; read(l, space); --- skip a space
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CPU: RTL Simulation
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-- read din value read(l, tmpdin, good_val); assert good_val REPORT bad din value ; clk <= tmpclk; ld <= tmpld; up_dwn <= tmpup_dwn; clk_en <= tmpclk_en; din <= tmpdin; END LOOP; ASSERT false REPORT Test complete ; WAIT; END PROCESS; END;
The beginning of the testbench declares entity testbench as an entity with no ports This is completely legal as the testbench is the topmost entity and does not interract with any other entities Next is the architecture declaration The architecture uses a number of packages including IEEE standard packages and counter The next section in the model declares the component for the DUT (Device Under Test), the counter The ports and types on this component should match the DUT Next, the local interconnect signals are declared After the architecture declaration section, the DUT component is instantiated and connected to the local interconnect signals A process called test is declared which contains the stimulus generation capability First, a number of local variables are declared to receive data from the TextIO procedures used to read the stimulus information from a file TextIO can only assign to variable objects not signals; therefore, local variables are assigned by the TextIO procedures, and these variables are assigned to the internal interconnect signals Inside the process is a single while loop that reads data from the stimulus file until an end-of-file condition is reached Each pass through the loop reads another line from the file and reads the appropriate data from that line The first data read from the line is the time that this vector is to be applied The process checks to make sure that the value read is a valid number If not, the line is discarded because it does not represent a valid stimulus line This allows comment lines to be inserted in the vector files If a valid number was not read, the process skips this iteration through the loop and goes to the next iteration using the next clause If the value read was a good number, then the vector is assumed to be valid The process reads each data value from the vector and applies the values to the locally declared variables
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