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In the counter example, the first value read is the clk signal The TextIO statement reads a STD_LOGIC value from line l and assigns the value read to variable tmpclk Later, the tmpclk variable is assigned to the signal clk The process continues to read a line, read a time value, wait until that time value occurs, read all vector values, and apply vector values until the end of the file is reached When the end of the file is reached, the loop terminates, an assertion message is written to standard output, and the process waits forever The WAIT statement after the assertion at the end of the loop doesn t have a termination condition and, therefore, waits forever, effectively stopping execution of this process The TEXTIO readline statement inside the while loop reads a vector line from a vector file Following is an example vector file:
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--- vector file for counter -- time clk ld up_dwn clk_en din 10 0001 0 20 1101 50 30 0001 0 40 1001 0 50 0001 0 60 1001 0 70 0001 0 80 1001 0 90 0001 0 100 1101 10 110 0001 0 120 1001 0 130 0001 0 140 1001 0 150 0001 0 160 1001 0
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The first two lines of the vector file do not start with valid numbers and are treated as comment lines Comment lines can be embedded anywhere in the file Comments can also be placed at the end of a vector because any data after the last field of the vector are ignored Each vector line starts with a time value and then contains a string of values to be assigned to the DUT at that time Spaces can be embedded between vector values if a corresponding read function exists in the while loop to skip the space For the stimulus only testbench, the test process reads a vector from the file and applies the stimulus to the DUT The stimulus only testbench does not check the output results of the DUT in reaction to the applied stimulus The stimulus only testbench is most useful for a quick check of a piece of a design that is easy for the designer to verify manually or for
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CPU: RTL Simulation
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early in the design process when no known good results exist to verify against When the results are verified, these results become the known good results to verify future versions or minor changes to the design
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A full testbench is very similar to a stimulus only testbench except that the full testbench also includes the capability to check the output of the DUT The full testbench applies the stimulus to the design and then examines the outputs of the design to see if the output results of the DUT match known good results Following is a full testbench for the counter:
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ENTITY testbench IS END; ------------------------------------------------------------- FULL TESTBENCH -- testbench for counter -- reads from file countertxt -----------------------------------------------------------LIBRARY ieee; USE ieeestd_logic_1164ALL; USE stdtextioALL; USE ieeestd_logic_textioall; USE WORKcount_typesall; ARCHITECTURE full OF testbench IS ------------------------------------ component declaration for counter ----------------------------------COMPONENT count PORT (clk : IN std_logic; ld : IN std_logic; up_dwn : IN std_logic; clk_en : IN std_logic; din : IN bit8; qout : INOUT bit8); END COMPONENT; SIGNAL clk, ld, up_dwn, clk_en : std_logic; SIGNAL qout, din : bit8;
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BEGIN -- instantiate the component uut: count PORT MAP(clk => clk, ld => ld,
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up_dwn => up_dwn, clk_en => clk_en, din => din, qout => qout);
Fourteen
-- provide stimulus and check the result test: PROCESS VARIABLE tmpclk, tmpld, tmpup_dwn, tmpclk_en : std_logic; VARIABLE tmpqout, tmpdin : bit8; FILE vector_file : text IS IN countertxt ; VARIABLE l : line; VARIABLE vector_time : time; VARIABLE r : real; VARIABLE good_number, good_val : boolean; VARIABLE space : character; BEGIN WHILE NOT endfile(vector_file) LOOP readline(vector_file, l); -- read the time from the beginning of the line -- skip the line if it doesn t start with a number read(l, r, good => good_number); NEXT WHEN NOT good_number; vector_time := r * 1 ns; IF (now < vector_time) THEN WAIT FOR vector_time - now; END IF; read(l, space); --- skip a space -- convert real number to time -- wait until the vector time
-- read clk value read(l, tmpclk, good_val); assert good_val REPORT bad clk value ; -- read ld value read(l, tmpld, good_val); assert good_val REPORT bad ld value ; -- read up_dwn value read(l, tmpup_dwn, good_val); assert good_val REPORT bad up_dwn value ; -- read clk_en value read(l, tmpclk_en, good_val); assert good_val REPORT bad clk_en value ;
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