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changed by another force command The input signals are all set to an initial value and the run command advances simulation time and runs the simulation All of the input values are propagated appropriately through the design After the run command has finished, the new input stimulus values are set up with more force commands, and the simulation is run again This process continues until all stimulus has been run through the design The write command near the end of the file writes the results of the simulation to a file The designer can analyze the output file to determine if the design is correct or use a file compare facility to automatically compare the DUT results to known good results The advantages of a simulator-specific testbench are that it is fairly quick and easy to generate, and it can be loaded and reloaded into the simulator without shutting the simulator down and starting over every time A simulation can be run, the results analyzed, simulation time reset to 0, a stimulus file loaded, and the simulator run again The disadvantage of the simulator-specific testbench is that the testbench is specific to one simulator and cannot be easily migrated If the design is to be passed to another design group using another simulator, the testbenches need to be rewritten in the new command language
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Hybrid testbenches do not utilize only one technique, but a combination of a number of techniques Hybrid testbenches can use a full testbench approach but have some of the stimulus data generated in the testbench rather than read from a file Hybrid testbenches can also mix simulator-specific commands with stimulus read from a file Following is a sample hybrid testbench:
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ENTITY testbench IS END; ------------------------------------------------------------- HYBRID Testbench -- testbench for 8-bit loadable updown counter -- reads from file countertxt -----------------------------------------------------------LIBRARY ieee; USE ieeestd_logic_1164ALL; USE stdtextioALL; USE ieeestd_logic_textioall;
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USE WORKcount_typesall; ARCHITECTURE hybrid OF testbench IS ------------------------------------ component declaration for counter ----------------------------------COMPONENT count PORT (clk : IN std_logic; ld : IN std_logic; up_dwn : IN std_logic; clk_en : IN std_logic; din : IN bit8; qout : INOUT bit8); END COMPONENT; SIGNAL ld, up_dwn, clk_en : std_logic; SIGNAL clk : std_logic := 0 ; SIGNAL qout, din : bit8; BEGIN -- instantiate the component uut: count PORT MAP(clk => clk, ld => ld, up_dwn => up_dwn, clk_en => clk_en, din => din, qout => qout); -- Generate the system clock clk <= not clk after 10 ns; -- provide stimulus and check the result test: PROCESS
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VARIABLE tmpclk, tmpld, tmpup_dwn, tmpclk_en : std_logic; VARIABLE tmpqout, tmpdin : bit8; FILE vector_file : text IS IN countertxt ; VARIABLE l : line; VARIABLE vector_time : time; VARIABLE r : real; VARIABLE good_number, good_val : boolean; VARIABLE space : character; BEGIN WHILE NOT endfile(vector_file) LOOP readline(vector_file, l); -- read the time from the beginning of the line -- skip the line if it doesn t start with a number
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read(l, r, good => good_number); NEXT WHEN NOT good_number; vector_time := r * 1 ns; IF (now < vector_time) THEN WAIT FOR vector_time - now; END IF; read(l, space); --- skip a space -- convert real number to time -- wait until the vector time
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-- read ld value read(l,tmpld, good_val); assert good_val REPORT bad ld value ; -- read up_dwn value read(l,tmpup_dwn, good_val); assert good_val REPORT bad up_dwn value ; -- read clk_en value read(l,tmpclk_en, good_val); assert good_val REPORT bad clk_en value ; read(l, space); --- skip a space
-- read din value read(l, tmpdin, good_val); assert good_val REPORT bad din value ; ld <= tmpld; up_dwn <= tmpup_dwn; clk_en <= tmpclk_en; din <= tmpdin; END LOOP; ASSERT false REPORT Test complete ; WAIT; END PROCESS; END;
The hybrid testbench example looks very similar to the stimulus only testbench example except that, right after the counter component instantiation, the system clock is generated by a signal assignment statement Signal clk is assigned the value of not clk after 10 nanoseconds This statement creates a periodic waveform with a period of 20 nanoseconds The testbench does not read signal clock from the vector file The vector file contains changes only on signals other than clock This results in a much smaller file that can be read much faster Following is the hybrid vector file:
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