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This creates the work library in the current working directory of the current disk After the library has been created, the VHDL source files for the design can be compiled into the target library To compile each of the files, the VCOM command must be run either from the GUI (Graphical User Interface) or from the command line Most of the operations of the simulator have a GUI method of performing the command line command This allows casual users as well as expert users to effectively use the simulator Normally, casual users use the GUI and experts use the command line and script interface
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To compile a file from the GUI, the file is selected in the compile dialog box as shown in Figure 14-4 The GUI includes a file browser that allows the designer to select the files to compile and then click the Compile button to compile the file To compile a file from the command line interface, the following command is issued:
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This checks that the VHDL syntax is correct and converts the VHDL syntax to the binary format needed to simulate the design Following is a complete script that compiles all of the files in the proper order:
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vcom vcom vcom vcom vcom vcom cpu_libvhd aluvhd compvhd regvhd shiftvhd controlvhd
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Figure 14-4 Compile VHDL Source Dialog Box
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After all of the files have been compiled, the design can be loaded into the simulator for verification This can be initiated from the GUI or from the command line with the following command:
vsim -lib work top behave
This command specifies the library (work), entity (top), and architecture (behave) or configuration to simulate After the design has been loaded, the simulator needs stimulus for the design and specification of what data to monitor For this simulation, the current_state, the memory interface, program counter, and other signals are monitored Figure 14-5 shows a waveform display of the reset sequence of the CPU From this display, we can verify that the CPU is functioning properly At time 0, the reset signal is set to a 1 value, which puts the CPU into state reset1, the first state of the reset sequence After the reset signal is set to 0 , the CPU can begin performing the reset sequence The two most interesting signals to examine are current_state and next_state Notice that, while the reset input is a 1 , the CPU remains in state reset1 After signal reset is set to a 0 , on the next rising edge of signal clock, current_state advances to state reset2 Each clock rising edge after that causes the CPU to advance to the next state At state reset3, the data bus receives the value 0000 to be used as the starting address for the first instruction At state reset4, register
Figure 14-5 Waveform Display of the Reset Sequence
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addreg is loaded with the data bus value so that the 0000 value can be used to drive the addr bus At state reset5, the data bus is driven with the instruction data from component mem at address 0 This data is then loaded into register instrreg in reset6 so that the control entity can use the instruction contents The next state after reset6 is the first execution step of the instruction that was just fetched from the memory Looking back at the description of the mem entity, we can see that the first instruction loads register 1 with the source address of the copy operation Figure 14-6 shows the waveform display after the reset sequence has completed and the first instruction has started to execute This instruction is a LoadI (Load Immediate) instruction that uses two words of the memory The instruction is shown here: LoadI 1, # 10
The first word of the instruction specifies the behavior of the instruction, and the second specifies the data to be loaded into the register specified by the instruction This instruction first puts the program counter value to the data bus so that the value can be incremented The program counter is then able to read the second word of the instruction that contains the data to be loaded into reg 1 During state execute, the program counter is incremented and the incremented value can be found as the output of the ALU aluout During states loadi2, loadi3, and loadi4, this value is transferred to register addreg and data is read from mem entity in state loadi5 During state loadi6, data from memory is loaded into register 1
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