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Scanner QR Code JIS X 0510 in C#.NET Figure 15-6 Set Order of Input Files

Figure 15-6 Set Order of Input Files
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is small enough, removing the hierarchy will create a smaller and faster design Finally IO pads will not be added to the design as the Altera place and route tool will do this automatically The optimize user interface with all the switches set is shown in Figure 15-8 Selection of the Optimize button will perform the optimization process and implement the specified design with Apex 20KE technology primitives The Report tab is used to generate area and timing reports An area report gives the size of the design based on the design implementation in the target technology To generate a report, select the Report Area
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CPU Design: Synthesis Results
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Figure 15-7 Set Clock Constraint to 30 Mhz
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button as shown in Figure 15-9 The report generated will look like the one shown below:
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->report_area -cell_usage -all_leafs ******************************************************* Cell: cpu View: rtl Library: work cpu ******************************************************* Cell Library References Total Area GND apex20e 1 x 1 1 GND
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Figure 15-8 Optimize Design
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TRI VCC alu apex20_lcell_normal comp control
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apex20e apex20e work apex20e work work
16 x 1 x 1 x 33 x 1 x 1 x
1 1 1 156 1 26 108 1 1 384
16 1 1 156 33 26 108 1 1 384
TRIs VCC GND LCs LCs LCs LCs GND VCC Memory Bits
CPU Design: Synthesis Results
Figure 15-9 Report Area
reg reg regarray_notri shift trireg_notri Number of ports :
work work work work work
1 x 1 x 1 x 1 x 3 x 37
11 1 16 1 1 128 1 16 1
11 1 16 1 1 128 1 48 3
LCs GND LCs GND VCC Memory Bits shift LCs GND
Number of nets : Number of instances : Number of references to this view: total accumulated area: DELAY flex10 8 x 198 61 0
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Number Number Number Number Number Number Number
of of of of of of of
GND : LCs : Memory Bits : TRIs : VCC : SHIFT : accumulated instances :
8 398 512 16 1 1 443
*********************************************** Device Utilization for EP20K200EFC484 *********************************************** Resource Used Avail Utilization ----------------------------------------------IOs 37 376 984% LCs 398 8320 478% Memory Bits 512 106496 048% ----------------------------------------------Info, Command 'report_area' finished successfully
The last step in the synthesis process is to write out a gate-level description for the optimized design For this example the output format used will be EDIF The common term for this output file is a netlist, because it describes the primitives used in the design and the signals (or nets short for networks) used to connect these primitives To generate the netlist select the Output tab, modify the name of the output file as necessary, and then select the Write button This is shown in Figure 15-10 This netlist will now be passed to the Altera place and route tools to create the actual implementation of the device This process is described in the next chapter
SUMMARY
In this chapter, we synthesized all of the VHDL RTL descriptions of the CPU and analyzed the results In the next chapter, we read the synthesized netlist into the place and route tools, and run the place and route to implement the design in the target technology
CPU Design: Synthesis Results
Figure 15-10
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CHAPTER
Place and Route
This chapter discusses the process of implementing the synthesis netlist of the CPU design into a target FPGA device The place and route tools read the netlist, extract the components and nets from the netlist, place the components on the target device, and interconnect the components using the specified interconnections After the place and route process is complete, the designer has an implementation of the design in the target technology The implementation still needs to be verified for logical and timing correctness
Figure 16-1 Place and Route Process
Synthesis Netlist Placement Routing
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No Yes Constraints Met
Place and Route Process
The place and route process places each macro from the synthesis netlist into an available location on the target silicon and connects the macros using routing resources available on the target silicon The place and route process is shown in Figure 16-1 The synthesis netlist is input to the placement process The placement process analyzes all of the macros used in the design and their connectivity to try to determine an optimal placement for the macros The placement algorithms take into account a number of technology-specific factors of the target technology to determine whether a particular placement is good or not After a trial placement and signal route is attempted, the design is analyzed with respect to timing constraints If the timing constraints are not met, the place and route software continues to try different placements and signal routing to try to meet the constraints Typical target devices have areas of the chip where logical functions are placed, and areas where interconnect signals are routed to connect the logical functions This is shown in Figure 16-2 The device is split into a number of logic areas with routing channels that surround the logic areas Logic areas contain the logical gates to implement the boolean function of the design Routing channels contain the signals that are used to connect the logical gates together For FPGA devices, the routing channels contain programmable interconnect wires FPGA devices use an onboard RAM to store the value of programmable switches that are used to form the signal interconnections By enabling the proper sets of pass transistor gates, signal interconnections between logic gates can be formed as shown in the example in Figure 16-3 To make a connection from logic block 1 to logic block 3, all of the switches shown need to be enabled with a logic 1 value The logic gates of the devices are connected to local routing signals that can be connected to more global routing signals by pass transistors that bridge the two signals The control signals of the pass transistors are stored in a loadable
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