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Reading QR-Code in C# Place and Route

Place and Route
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Figure 16-2 FPGA Chip Architecture
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Routing Channels
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Logic Area
Logic Area
Figure 16-3 Logic Block Interconnection
1 Logic Block 1 1 Logic Block 2 1 1 Logic Block 3
RAM The place and route tool generates the RAM image to be loaded into the RAM on the device The routing channels contain vertical and horizontal lines The horizontal wires connect devices within a row, while the vertical lines allow connections across rows Most routing channels contain wires of different
Figure 16-4 Vertical and Horizontal Routing
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Connects short segments together
lengths that allow connections to adjacent logic areas Sometimes, longer connections are needed, and either a longer line must be used or shorter lines must be connected together to form the connection This is shown in Figure 16-4 The job of the place and route tool is to create the programming files that will be used to specify the logic function of the logic macros in the logic areas and the switch programming of the wires used to connect the macros together Too many switches on a routed signal can cause some negative performance effects Each switch adds capacitance and resistance to the routed signal After only a few connections, signals start to slow significantly because of the capacitance and resistance of the line The place and route tool, therefore, must try to minimize long connections and the number of switches for a particular signal to create designs with the highest speed To get the highest utilization, the place and route tools need to pack as many of the logical functions into a logic area as possible and then use as much local routing resources as possible to connect these functions The place and route tools can make tradeoffs if the speed-critical signals are known ahead of time and are implemented using the highest speed interconnect signals The placement algorithm also tries to place logical gates on the critical path close to each other so that local interconnect can be used to connect the gates Local interconnect is usually very fast because the wires are short Short wires have less capacitance and resistance and, therefore, can operate at much higher speeds
Place and Route
Placing and Routing the Device
The target device for the CPU design, as mentioned in earlier chapters, is an FPGA device The device used is the Apex 20KE architecture from Altera The place and route tools used with the Apex 20KE architecture are in the Quartus toolset Quartus is a set of tools that includes not only place and route, but VHDL entry, VHDL simulation, gate-level simulation, and timing analysis The first step in the process is to compile the design into the place and route environment
Setting Up a Project
Most tools that work on a design with multiple data descriptions have a project manager to keep all of the files for that design in one place This facilitates file management of the design The first step in the place and route process is to set up a project In the case of the Quartus environment, the project is usually named the same as the output EDIF file from synthesis The Quartus user interface is shown in Figure 16-5 Selecting the File Project Wizard menu item will bring up a wizard that walks the user through the creation of a new project The first pane
Figure 16-5 Quartus User Interface
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of this wizard is shown in Figure 16-6 This introduces the concept of a wizard to the user The next step is to select the directory that contains the EDIF file that was generated by Leonardo Spectrum In Figure 16-7, the directory of the EDIF file, the name of the project, and the name of the top-level entity are specified It is usually a good idea to make the name of the project and top-level entity the same The next step in the wizard is to add the EDIF file to the project Clicking the next button brings up the interface shown in Figure 16-8 Using the button with the three dots, the file user can find the file and add it to the project The next step is to specify the EDA settings so that the EDIF file can be properly interpreted Use the Project EDA Tool Settings menu item to invoke the EDA Tool Settings Dialog box shown in Figure 16-9 The Design entry/synthesis tool item needs to be changed to Leonardo Spectrum The next step is to select the physical device to implement Remember we will use the EP20K200EFC484 device This device is selected from the list of devices shown in Figure 16-10 The Chips and Devices tab displays a list of devices to select from The list includes the device and the speed grade Finally the device pins need to be assigned to the ports of the VHDL design The cpu clock port must be assigned to a pad driver that is capable
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