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VITAL Implementation
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VITAL descriptions follow a standard style and make use of standard functions and procedures from two VITAL packages The VITAL Timing
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CPU:Vital Simulation
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Package contains procedures and functions for accurate delay modeling, timing checks, and timing error reporting The VITAL Primitives Package contains built-in primitives that are optimized for simulator performance Most VITAL-compliant simulators build the primitives package into the simulator for optimum performance VITAL contains two styles of modeling that can be back-annotated with SDF timing data for timing-accurate simulation The first style, VITAL level 1, uses only VITAL primitives for modeling the behavior of the design The second, VITAL level 0, has the capability to back-annotate timing, but uses behavioral statements to describe the functionality of the design VITAL level 1 descriptions can be accelerated by VITAL-compliant simulators because the constructs used are built into the simulator VITAL level 0 descriptions may not be accelerated because these descriptions use behavioral constructs which may not be built in
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Simple VITAL Model
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To understand how the VITAL modeling process works, a simple VITAL model is examined The model describes the behavior of a 2-input AND gate The symbol for the AND gate is shown in Figure 17-3 The AND gate has two inputs, in1 and in2, and an output y When modeled with VITAL, this device has an input delay on inputs in1 and
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in1 Input Delay
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Figure 17-3 VITAL AND Gate
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in1 y
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Output Delay int2 -> y
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Seventeen
in2, and pin-to-pin delays from input in1 to output y and from input in2 to output y
Following is the VITAL model that implements the functionality of the
AND2 device: ----- CELL AND2 ----library IEEE; use IEEESTD_LOGIC_1164all; use IEEEVITAL_Timingall; library alt_vtl; use alt_vtlSUPPORTall; -- entity declaration -entity AND2 is generic( TimingChecksOn: Boolean := True; XGenerationOn: Boolean := False; InstancePath: STRING := * ; tpd_IN1_Y : VitalDelayType01 := tpd_IN2_Y : VitalDelayType01 := tipd_IN1 : VitalDelayType01 := tipd_IN2 : VitalDelayType01 :=
DefPropDelay01; DefPropDelay01; DefPropDelay01; DefPropDelay01);
port( Y : out STD_LOGIC; IN1 : in STD_LOGIC; IN2 : in STD_LOGIC); attribute VITAL_LEVEL0 of AND2 : entity is TRUE; end AND2; -- architecture body -architecture AltVITAL of AND2 is attribute VITAL_LEVEL1 of AltVITAL : architecture is TRUE; SIGNAL IN1_ipd : STD_ULOGIC := U ; SIGNAL IN2_ipd : STD_ULOGIC := U ; begin ---------------------- INPUT PATH DELAYs --------------------WireDelay : block begin VitalWireDelay (IN1_ipd, IN1, tipd_IN1); VitalWireDelay (IN2_ipd, IN2, tipd_IN2); end block; --------------------- BEHAVIOR SECTION -------------------VITALBehavior : process (IN1_ipd, IN2_ipd)
CPU:Vital Simulation
-- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := VARIABLE Results : (others => X ); ALIAS Y_zd : STD_ULOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin -------------------------- Functionality Section ------------------------Y_zd := (IN2_ipd) AND (IN1_ipd);
----------------------- Path Delay Section ---------------------VitalPathDelay01 ( OutSignal => Y, OutSignalName => Y , OutTemp => Y_zd, Paths => (0 => (IN1_ipd last_event, tpd_IN1_Y, Paths => (0 => (TRUE), Paths => (1 => (IN2_ipd last_event, tpd_IN2_Y, Paths => (1 => (TRUE)), GlitchData => Y_GlitchData, Mode => DefGlitchMode, XOn => DefGlitchXOn);
end process; end AltVITAL; configuration CFG_AND2_VITAL of AND2 is for AltVITAL end for; end CFG_AND2_VITAL;
The model looks like standard VHDL with some different packages included In fact, the model is standard VHDL The entity contains declarations for the STD_1164 packages for the signal logic types, but also contains USE clauses for the VITAL timing package The VITAL timing package is needed in the entity for AND2 to provide the type declarations for the entity generics The entity statement contains four generics that are used to pass delay information to the model Each of the generics has a prefix that represents the type of the delay Generic tipd_in1 is an input delay for input in1 Generic tipd_in2 is an input delay for input in2 Generic
Seventeen
tpd_in1_y models the pin-to-pin delay from input in1 to output y Generic tidp_in2_y models the pin-to-pin delay from input in2 to output y
The timing information passed to these generics comes from the SDF file generated by the place and route tool Each of the delays passed to the entity is instance specific Each of the generics has a type associated with it that represents how many delay values can be held In this example, the generic contains two values Delay tr01 represents the delay value when the signal changes from a 0 to 1 value Delay tr10 represents the delay when the signal changes from a 1 to 0 value The entity also contains other generics that control functionality of the VITAL model This example contains a generic called TimingChecksOn that controls whether or not the timing check functions in the VITAL model are executed or not Finally, the entity contains the input and output ports for the model
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