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VITAL Architecture
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The architecture for the VITAL model contains four distinct code areas These are the wire delay section, the timing violation section, the function description section, and the path delay section Not all models contain all of these sections Some models are purely combinational and do not need timing check sections
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Wire Delay Section
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The first section of the architecture is the wire delay section The AND2 architecture starts with a number of library declarations; but notice that the architecture also uses the VITAL primitives package After the architecture statement, the architecture declares two local signals, in1_ipd and in2_ipd, and an attribute The two signals are used to delay the input signals to the entity The delay values applied to the two input signals represent the wiring delays to connect the physical gates together For instance, in Figure 17-4, gate U1 drives gates U2 and U3 The wiring from gate U1 to gate U2 causes 8 nanoseconds of delay in the path, but the wiring from U1 to U3 causes 10 nanoseconds of delay in the path With separate input delay values for each input, the wiring delays can be modeled correctly
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CPU:Vital Simulation
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Figure 17-4 Wire Delay Representation
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Attribute VitalLevel1 specifies that the VITAL model is level 1 compliant Level 1 models are modeled only with VITAL primitives and can be accelerated Some simulators have compliance checkers that can validate level 1 compliance The architecture contains a block labeled WireDelay which contains the VHDL description that actually delays the input signals The block contains a call to the VitalWireDelay procedure for each input port The VitalWireDelay procedure delays the input ports by the value passed to the appropriate generic used in the procedure call In this example, generic tipd_in1 is used to delay input in1, and generic tipd_in2 is used to delay input in2 After the wire delay section is the timing check section This example has no timing check section because it is a purely combinational gate model The next section is the functionality section This section contains the statements that model the behavior of the device This section starts with a process labeled VitalBehavior Notice that the process is sensitive to the delayed versions of the two input signals, in1_ipd and in2_ipd There are a number of local variables declared and a statement that performs an AND function of the two inputs This AND function can be built into the simulator so that execution can be accelerated The last section of the architecture starts with the VitalPathDelay procedure call This section is the path delay section This section schedules the new logic values calculated in the functionality section to occur after the appropriate delay This section consists of a VitalPathDelay01 procedure call for each output from the entity
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The VitalPathDelay01 procedure has a number of parameters passed to it These parameters are used to control what kind of glitch behavior is wanted, the delays to be used, and the temporary data used to store signal information In this example, the VitalPathDelay procedure is passed the following parameters: I OutSignal The signal to have the new value placed on it I OutSignalName The name of the output signal to be used in glitch reporting or error reporting I OutTemp A temporary signal used to store the current value of the signal for comparison I Paths An array used to store delay information There is a table entry for each delay arc through the device I GlitchData A temporary storage area used to store signal state and transition information for use in calculating glitches I Mode Specifies the type of glitch behavior wanted I GlitchKind Specifies the kind of glitches generated, OnEvent or OnDetect
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