CPU:Vital Simulation in Visual C#

Decoder QR Code JIS X 0510 in Visual C# CPU:Vital Simulation

-ready : IN std_logic; -reset : IN std_logic; -rw : OUT std_logic; -vma : OUT std_logic); --END cpu; ARCHITECTURE EPF10K10TC144_a3 OF cpu IS SIGNAL gnd : std_logic := 0 ; SIGNAL vcc : std_logic := 1 ; SIGNAL

To compile the VCOMPONENTS package into library alt_vtl, the following commands are executed in ModelSim:

Because there are no other library declarations for the actual vital library, the vital library entities need to be compiled into the working library to be visible Following is the command to perform this step:

After these two files have been compiled, the VITAL netlist can be compiled into the working library The following command compiles the netlist:

We still need to simulate design TOP to verify the gate-level implementation of the CPU However, this time, the CPU RTL description is replaced with a VITAL description of the CPU This can be accomplished by two different methods The first involves compilation order, and the second is by direct specification Remember that the last architecture compiled is used by default for an entity By compiling architecture EPF10K10TC144_a3 last, this architecture is used for entity cpu The other method is to write a configuration for architecture top that specifies exactly which architecture is to be used The following example shows two configuration statements for the two different implementations of the CPU:

configuration topconrtl of top is for behave for U1 : cpu use entity workcpu(behave); end for;

end for; end topconrtl;

configuration topconstruct of top is for behave for U1 : cpu use entity workcpu(EPF10K10TC144_a3); end for; end for; end topconstruct;

Configuration topconrtl specifies the rtl implementation configuration for entity top, and configuration topconstruct specifies the structural implementation Notice that the structural architecture was named the same as the device that was implemented by the place and route tools To complete the simulation setup process, the final compilations needed are shown here:

After these steps, the design is ready for simulation To load the design into the simulator, the following command is executed:

The simulator brings up its windows and begins the simulation If the simulation is run ahead 500 nanoseconds, we can see the CPU start the reset sequence as instructions are fetched This is shown in Figure 17-5

Running the simulation through the entire process verifies the functionality of the placed and routed design To verify the timing and functionality, we need to back-annotate the timing from place and route to the simulation

To run timing back-annotated simulation, we don t need to recompile We only need to specify to the simulator which SDF file to read This is done by the following command:

This command tells the simulator to back-annotate the VITAL simulation of the CPU design with SDF file cpuoutsdf created by the place and route tools After this command has executed, the simulation is invoked, and the SDF file is back-annotated to component U1 (cpu) and simulation started Running the simulation produces the waveform shown in Figure 17-6 The back-annotated delays are seen on the waveforms for addr and data around time 400 nanoseconds Notice that, instead of one transition, the waveforms have a number of transitions that finally settle out Using this timing information, the designer can now increase the clock speed

until the design stops working to determine the maximum speed that the design will run By running the design through the entire simulation, the functionality and timing of the design can be verified for correctness When the design meets the functionality and timing requirements, the design can be signed off and built

In this chapter, we examined VITAL simulation and how to perform VITAL simulation on the CPU design The rest of the book contains useful appendices that describe some of the standard types, functions, and procedures used throughout the book