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Standard Logic Package
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FUNCTION not RETURN UX01; ( l : std_ulogic
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-------------------------------------------------------- vectorized overloaded logical operators ------------------------------------------------------FUNCTION and ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION and ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION nand ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION nand ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION or ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION or ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION nor ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION nor ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION xor ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION xor ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; ---------------------------------------------------------------------Note : The declaration and implementation of the xnor function is specifically commented until at which time the VHDL language has been officially adopted as containing such a function At such a point, the following comments may be removed along with this notice without further official ballotting of this std_logic_1164 package It is the intent of this effort to provide such a function once it becomes available in the VHDL standard ------------------------------------------------------function xnor ( l, r : std_logic_vector ) return std_logic_vector; function xnor ( l, r : std_ulogic_vector ) return std_ulogic_vector; FUNCTION not ( l : std_logic_vector ) RETURN std_logic_vector; FUNCTION not ( l : std_ulogic_vector ) RETURN std_ulogic_vector; -------------------------------------------------------- conversion functions ------------------------------------------------------FUNCTION To_bit ( s : std_ulogic; xmap : BIT := 0 ) RETURN BIT; FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := 0 ) RETURN BIT_VECTOR;
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Appendix A:
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Standard Logic Package
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FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := 0 ) RETURN BIT_VECTOR; FUNCTION To_StdULogic RETURN std_ulogic; FUNCTION To_StdLogicVector RETURN std_logic_vector; FUNCTION To_StdLogicVector RETURN std_logic_vector; FUNCTION To_StdULogicVector RETURN std_ulogic_vector; FUNCTION To_StdULogicVector RETURN std_ulogic_vector; ( b : BIT ( b : BIT_VECTOR ) )
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( s : std_ulogic_vector ) ( b : BIT_VECTOR ( s : std_logic_vector ) )
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-------------------------------------------------------- strength strippers and type convertors ------------------------------------------------------FUNCTION RETURN FUNCTION RETURN FUNCTION RETURN FUNCTION RETURN FUNCTION RETURN FUNCTION RETURN FUNCTION RETURN FUNCTION RETURN FUNCTION RETURN FUNCTION RETURN FUNCTION RETURN FUNCTION RETURN FUNCTION RETURN FUNCTION RETURN FUNCTION RETURN FUNCTION RETURN FUNCTION RETURN FUNCTION RETURN To_X01 ( s : std_logic_vector std_logic_vector; To_X01 ( s : std_ulogic_vector std_ulogic_vector; To_X01 ( s : std_ulogic X01; To_X01 ( b : BIT_VECTOR std_logic_vector; To_X01 ( b : BIT_VECTOR std_ulogic_vector; To_X01 ( b : BIT X01; To_X01Z ( s : std_logic_vector std_logic_vector; To_X01Z ( s : std_ulogic_vector std_ulogic_vector; To_X01Z ( s : std_ulogic X01Z; To_X01Z ( b : BIT_VECTOR std_logic_vector; To_X01Z ( b : BIT_VECTOR std_ulogic_vector; To_X01Z ( b : BIT X01Z; To_UX01 std_logic_vector; To_UX01 std_ulogic_vector; To_UX01 UX01; To_UX01 std_logic_vector; To_UX01 std_ulogic_vector; To_UX01 UX01; ( s : std_logic_vector ) ) ) ) ) ) ) ) ) ) ) ) )
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( s : std_ulogic_vector ) ( s : std_ulogic ( b : BIT_VECTOR ( b : BIT_VECTOR ( b : BIT ) ) ) )
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-------------------------------------------------------- edge detection -------------------------------------------------------
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Appendix A:
Standard Logic Package
FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN; FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN; -------------------------------------------------------- object contains an unknown ------------------------------------------------------FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN; FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN; FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN; END std_logic_1164; ------------------------------------------------------------------------------------------------: std_logic_1164 multi-value logic system : This package shall be compiled into a : library symbolically named IEEE : Developers : IEEE model standards group (par 1164) Purpose : This package defines a standard for : designers to use in describing the : interconnection data types used in vhdl : modeling : Limitation : The logic system defined in this : package may be insufficient for modeling : switched transistors, since such a : requirement is out of the scope of this : effort Furthermore, mathematics, : primitives, timing standards, etc are : considered orthogonal issues as it : relates to this package and are : therefore beyond the scope of this : effort : Note : No declarations or definitions shall be : included in, or excluded from this : package The package declaration : defines the types, subtypes and : declarations of std_logic_1164 The : std_logic_1164 package body shall be : considered the formal definition of the : semantics of this package Tool : developers may choose to implement the : package body in the most efficient : manner available to them : -------------------------------------------------------modification history : -------------------------------------------------------version | mod date:| v4200 | 01/02/91 | -------------------------------------------------------Title Library
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