SLL shift left logical in C#.NET

Reader QR in C#.NET SLL shift left logical

q <= a SLL b; q equals a shifted left by b bits and filled on the right with the value a left If b is negative then a is shifted right

q <= a SRL b; q equals a shifted right by b bits and filled on the left with the value a left If b is negative then a is shifted left

q <= a SLA b; q equals a shifted left by b bits and filled on the right with a(a right) If b is negative then a is shifted right

q <= a SRA b; q equals a shifted right by b bits and filled on the left with a(a left) If b is negative then a is shifted left

q <= a ROL b;

q equals a rotated left by b bits Instead of filling the right b bits with a value, the b bits that were shifted off the left end are copied to the right of the shifted a bits An array that originally contained ABCD and is rotated left one bit will become BCDA

q <= a ROR b; q equals a rotated right by b bits Instead of filling the left b bits with a value, the b bits that were shifted off the right end are copied to the left of the shifted a bits An array that originally contained ABCD and is rotated right one bit will become DABC

As part of the VHDL93 syntax update a number of the language end clauses were modified to become more consistent All of the clauses now include the beginning clause identifier For instance in VHDL87 the entity clause was as shown here:

ENTITY test IS --END test;

In VHDL93 the same construct can optionally look as follows:

ENTITY test IS --END ENTITY test;

Notice that the END clause contains the starting ENTITY clause Including the keyword ENTITY in the END clause is optional but allowed in VHDL93 The same holds true for the architecture, package, package body, configuration, component, block, process, record, case, if, procedure, and generate statement Examples are shown here:

ARCHITECTURE behave OF test IS BEGIN --END ARCHITECTURE behave; PACKAGE mypack IS --END PACKAGE mypack; PACKAGE BODY mypack IS --END PACKAGE BODY mypack; CONFIGURATION chip OF processor IS --END CONFIGURATION chip;

COMPONENT memory IS -- notice addition of IS at end of component clause -END COMPONENT memory; block1 : BLOCK IS BEGIN -END BLOCK block1; proc1: PROCESS(clk, din) IS -- notice addition of IS at end of process clause BEGIN -END PROCESS proc1; RECORD myrec IS -END RECORD myrec; CASE selector IS -END CASE selector; lab: IF expr THEN -END IF lab; PROCEDURE convertval() IS BEGIN -END PROCEDURE convertval; g1: FOR k IN 0 TO 7 GENERATE BEGIN -END GENERATE g1; loop1: FOR k IN 0 TO 7 LOOP -END LOOP loop1;

In VHDL87 it was sometimes difficult to describe exactly the behavior required with a concurrent signal assignment statement For instance, there are cases where the modeler wants the value to remain unchanged if certain conditions are met In VHDL87 this can be accomplished with the following statement:

new_state <= state5 WHEN current_state = state1 AND input = 7 ELSE state6 WHEN current_state = state5 AND input = 8 ELSE state7 WHEN current_state = state2 AND input = 9 ELSE new_state;

If none of the above conditions are met the designer has to assign the current value, new_state to new_state to ensure no value change This produces the correct value but has a side effect that a transaction is generated on signal new_state Any behaviors sensitive to transactions on new_state will be evaluated and may update their values causing further activity when none is wanted VHDL93 has the new keyword UNAFFECTED that allows no change on a signal UNAFFECTED causes no value changes or transactions on the signal The same statement above rewritten to include this new feature looks as follows:

new_state <= state5 WHEN current_state = state1 AND input = 7 ELSE state6 WHEN current_state = state5 AND input = 8 ELSE state7 WHEN current_state = state2 AND input = 9 ELSE UNAFFECTED;