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In this example, signal qbus is declared in two blocks The interesting feature of this model is that one of the blocks is contained in the other It would seem that BLK2 has access to two signals called qbus the first from the local declaration of qbus in the declaration section of BLK2 and the second from the declaration section of BLK1 BLK1 is also the parent block of BLK2 However, BLK2 sees only the qbus signal from the declaration in BLK2 The qbus signal from BLK1 has been overridden by a declaration of the same name in BLK2 The qbus signal from BLK1 can be seen inside of BLK2, if the name of signal qbus is qualified with the block name For instance, in this example, to reference signal qbus from BLK1, use BLK1qbus In general, this can be a very confusing method of modeling The problem stems from the fact that you are never quite sure which qbus is being referenced at a given time without fully analyzing all of the declarations carefully As mentioned earlier, blocks are self-contained regions of the model But blocks are unique because a block can contain ports and generics This allows the designer to remap signals and generics external to the block to signals and generics inside the block But why, as designers, would we want to do that The capability of ports and generics on blocks allows the designer to reuse blocks written for another purpose in a new design For instance, let s assume that you are upgrading a CPU design and need extra functionality in the ALU section Let s also assume that another designer has a new ALU model that performs the functionality needed The only trouble with the new ALU model is that the interface port names and generic names are different than the names that exist in the design being upgraded With the port and generic mapping capability within blocks, this is no problem Map the signal names and the generic parameters in the design being upgraded to ports and generics created for the new ALU block Following is an example illustrating this:
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PACKAGE math IS TYPE tw32 IS ARRAY(31 DOWNTO 0) OF std_logic; FUNCTION tw_add(a, b : tw32) RETURN tw32; FUNCTION tw_sub(a, b : tw32) RETURN tw32; END math;
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USE WORKmathALL; LIBRARY IEEE; USE IEEEstd_logic_1164ALL; ENTITY cpu IS PORT( clk, interrupt : IN std_logic; PORT( addr : OUT tw32; cont : IN INTEGER; PORT( data : INOUT tw32 ); END cpu;
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ARCHITECTURE cpu_blk OF cpu IS SIGNAL ibus, dbus : tw32; BEGIN ALU : BLOCK PORT( abus, bbus : IN tw32; PORT( d_out : OUT tw32; PORT( ctbus : IN INTEGER); PORT MAP ( abus => ibus, bbus => dbus, d_out => data, PORT MAP ( ctbus => cont); SIGNAL qbus : tw32; BEGIN d_out <= tw_add(abus, bbus) WHEN ctbus = 0 ELSE d_out <= tw_sub(abus, bbus) WHEN ctbus = 1 ELSE d_out <= abus; END BLOCK ALU; END cpu_blk;
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Basically, this is the same model shown earlier except for the port and port map statements in the ALU block declaration section The port statement declares the number of ports used for the block, the direction of the ports, and the type of the ports The port map statement maps the new ports with signals or ports that exist outside of the block Port abus is mapped to architecture CPU_BLK local signal ibus; port bbus is mapped to dbus Ports d_out and ctbus are mapped to external ports of the entity Mapping implies a connection between the port and the external signal such that, whenever there is a change in value on the signal connected to a port, the port value changes to the new value If a change occurs in the signal ibus, the new value of ibus is passed into the ALU block and port abus obtains the new value The same is true for all ports
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