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Block statements have another interesting behavior known as guarded blocks A guarded block contains a guard expression that can enable and disable drivers inside the block The guard expression is a boolean expression: when true, drivers contained in the block are enabled, and when false, the drivers are disabled Let s look at the following example to show
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LIBRARY IEEE; USE IEEEstd_logic_1164ALL; ENTITY latch IS PORT( d, clk : IN std_logic; q, qb : OUT std_logic); END latch; ARCHITECTURE latch_guard OF latch IS BEGIN G1 : BLOCK( clk = 1 ) BEGIN q <= GUARDED d AFTER 5 ns; qb <= GUARDED NOT(d) AFTER 7 ns; END BLOCK G1; END latch_guard;
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This model illustrates how a latch model could be written using a guarded block This is a very simple-minded model; however, more complex and more accurate models will be shown later The entity declares the four ports needed for the latch, and the architecture has only one statement in it The statement is a guarded block statement A guarded block statement looks like a typical block statement, except for the guard expression after the keyword BLOCK The guard expression in this example is (clk = 1 ) This is a boolean expression that returns TRUE when clk is equal to a 1 value and FALSE when clk is equal to any other value When the guard expression is true, all of the drivers of guarded signal assignment statements are enabled, or turned on When the guard expression is false, all of the drivers of guarded signal assignment statements are disabled, or turned off There are two guarded signal assignment statements in this model: One is the statement that assigns a value to q and the other is the statement that assigns a value to qb A guarded signal assignment statement is recognized by the keyword GUARDED between the <= and the expression part of the statement When port clk of the entity has the value 1 , the guard expression is true, and the value of input d is scheduled on the q output after 5 nanoseconds, and the NOT value of d is scheduled on the qb output after 7 nanoseconds When port clk has the value 0 or any other legal value of the type, outputs q and qb turn off and the output value of the signal is determined by the default value assigned by the resolution function When clk is not equal to 1 , the drivers created by the signal assignments for q and qb in this architecture are effectively turned off The drivers do not contribute to the overall value of the signal Signal assignments can be guarded by using the keyword GUARDED A
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new signal is implicitly declared in the block whenever a block has a guard expression This signal is called GUARD Its value is the value of the guard expression This signal can be used to trigger other processes to occur Blocks are useful for partitioning the design into smaller, more manageable units They allow the designer the flexibility to create large designs from smaller building blocks and provide a convenient method of controlling the drivers on a signal
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In the first chapter, concepts of structurally building models were discussed This chapter is the first of many that discusses behavioral modeling In this chapter, we discussed: I How signal assignments are the most basic form of behavioral modeling I Signal assignment statements can be selected or conditional I Signal assignment statements can contain delays I VHDL contains inertial delay and transport delay I Simulation delta time points are used to order events in time I Drivers on a signal are created by signal assignment statements I Generics are used to pass data to entities I Block statements allow grouping within an entity I Guarded block statements allow the capability of turning off drivers within a block
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