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Sequential Processing
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WAIT UNTIL sendA = 1;
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Execution stops at the first WAIT statement of the process even though the expression sendA = 0 is satisfied by the first signal assignment of signal sendA This is because the WAIT statement needs an event to occur on signal sendA to cause the expression to be evaluated Both processes are now waiting on each other Neither process can continue because they are both waiting for a signal set by the other process If a time-out interval is inserted on each WAIT statement, execution can be allowed to continue There is one catch to this last statement Execution continues when the condition is not met An ASSERT statement can be added to check for continuation of the process without the condition being met The following example shows the architecture wait_example rewritten to include timeout clauses:
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ARCHITECTURE wait_timeout OF wait_example IS SIGNAL sendA, sendB : std_logic; BEGIN A : PROCESS BEGIN WAIT UNTIL (sendB = 1 ) FOR 1 us; ASSERT (sendB = 1 ) REPORT sendB timed out at 1 SEVERITY ERROR; sendA <= 1 AFTER 10 ns; WAIT UNTIL (sendB = 0 ) FOR 1 us; ASSERT (sendB = 0 ) REPORT sendB timed out at 0 SEVERITY ERROR; sendA <= 0 AFTER 10 ns; END PROCESS A; B : PROCESS BEGIN WAIT UNTIL (sendA = 0 ) FOR 1 us; ASSERT (sendA = 0 ) REPORT sendA timed out at 0 SEVERITY ERROR; sendB <= 0 AFTER 10 ns; WAIT UNTIL (sendA = 1 ) FOR 1 us; ASSERT (sendA = 1 )
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REPORT sendA timed out at 1 SEVERITY ERROR; sendB <= 1 AFTER 10 ns; end PROCESS B; END wait_timeout;
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Each of the WAIT statements now has a time-out expression specified as 1 usec However, if the time out does happen, the ASSERT statement reports an error that the WAIT statement in question has timed out
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Sensitivity List Versus WAIT Statement
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A process with a sensitivity list is an implicit WAIT ON the signals in the sensitivity list This is shown by the following example:
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PROCESS (clk) VARIABLE last_clk : std_logic := X ; BEGIN IF (clk /= last_clk ) AND (clk = 1 ) THEN q <= din AFTER 25 ns; END IF; last_clk := clk; END PROCESS;
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This example can be rewritten using a WAIT statement:
PROCESS VARIABLE last_clk : std_logic := X ; BEGIN IF (clk /= last_clk ) AND (clk = 1 ) THEN q <= din AFTER 25 ns; END IF; last_clk := clk; WAIT ON clk; END PROCESS;
The WAIT statement at the end of the process is equivalent to the sensitivity list at the beginning of the process But why is the WAIT statement at the end of the process and not at the beginning During initialization of the simulator, all processes are executed once To mimic the behavior of the sensitivity list, the WAIT statement must be at the end of the process to allow the PROCESS statement to execute once
Sequential Processing
Concurrent Assignment Problem
One of the problems that most designers using sequential signal assignment statements encounter is that the value assigned in the last statement does not appear immediately This can cause erroneous behavior in the model if the designer is depending on the new value An example of this problem is shown here:
LIBRARY IEEE; USE IEEEstd_logic_1164ALL; ENTITY mux IS PORT (I0, I1, I2, I3, A, B : IN std_logic; PORT (Q : OUT std_logic); END mux; ARCHITECTURE mux_behave OF mux IS SIGNAL sel : INTEGER RANGE 0 TO 3; BEGIN B : PROCESS(A, B, I0, I1, I2, I3) BEGIN sel <= 0; IF (A = 1 ) THEN sel <= sel + 1; END IF; IF (B = 1 ) THEN sel <= sel + 2; END IF; CASE sel IS WHEN 0 => Q <= I0; WHEN 1 => Q <= I1; WHEN 2 => Q <= I2; WHEN 3 => Q <= I3; END CASE; END PROCESS; END mux_behave;
This model is for a 4 to 1 multiplexer Depending on the values of A and B, one of the four inputs (I0 to I3) is transferred to output Q The architecture starts processing by initializing internal signal sel to the value 0 Then, based on the values of A and B, the values 1 or 2 are added to sel to select the correct input Finally, a CASE statement selected by the value of sel transfers the value of the input to output Q This architecture does not work as presently implemented The value of signal sel will never be initialized by the first line in the architecture:
sel <= 0;
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