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Passive processes are processes that exist in the entity statement part of an entity They are different from a normal process in that no signal assignment is allowed These processes are used to do all sorts of checking functions For instance, one good use of a passive process is to check the data setup time on a flip-flop The advantage of the passive process over the example discussed in the ASSERT statement section is that, because the passive process exists in the entity, it can be applied to any architecture of the entity Take a look at the following example:
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LIBRARY IEEE; USE IEEEstd_logic_1164ALL; ENTITY dff IS PORT( CLK, din : IN std_logic; PORT( Q, QB : OUT std_logic); BEGIN PROCESS(CLK, din) VARIABLE last_d_change : TIME := 0 ns; VARIABLE last_clk, last_d_value : std_logic := X ; BEGIN IF (din /= last_d_value) THEN last_d_change := now; last_d_value := din; END IF; IF (CLK /= last_clk) THEN IF (CLK = 1 ) THEN ASSERT(now - last_d_change >= 15 ns) REPORT setup error SEVERITY ERROR; END IF; last_clk := CLK; END IF; END PROCESS; END dff; ARCHITECTURE behave OF dff IS BEGIN END behave; ARCHITECTURE struct OF dff IS BEGIN
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END struct; ARCHITECTURE switch OF dff IS BEGIN END switch;
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This example shows the entity for a D flip-flop with a passive process included in the entity that performs a data setup check with respect to the clock This setup check function was described in detail in the ASSERT statement description What this example shows is that, when the setup check function is contained in the entity statement part, each of the architectures for the entity have the data setup check performed automatically Without this functionality, each of the architectures would have to have the setup check code included This introduces more code to maintain and can introduce inconsistencies between architectures The only restriction on these processes, as mentioned earlier, is that no signal assignment is allowed in a passive process In the preceding example, a process statement was used to illustrate a passive process A passive process can also exist as a concurrent statement that does not do any signal assignment Examples of such statements are concurrent ASSERT statements and concurrent subprogram invocations An example of two concurrent ASSERT statements as passive processes are shown here:
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ENTITY adder IS PORT( A, B : IN INTEGER; PORT( X : OUT INTEGER); BEGIN ASSERT (A < 256) REPORT A out of range SEVERITY ERROR; ASSERT (B < 256) REPORT B out of range SEVERITY ERROR; END adder;
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The first ASSERT statement checks to make sure that input A is not out of range, and the second assertion checks that input B is not out of the range of the adder Each of these statements acts as an individual process
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that is sensitive to the signal in its expression For instance, the first assertion is sensitive to signal A because that signal is contained in its expression
SUMMARY
In this chapter, we discussed the following: I How process statements are concurrent statements that delineate areas of sequential statements I How process statements can be used to control when a process is activated I How signal assignments are scheduled and variable assignments happen immediately within a process statement I How IF, CASE, and LOOP statements can be used to control the flow of execution within a model I How ASSERTION statements can be used to check for error conditions or report information to the user I The three forms of the WAIT statement How WAIT UNTIL is used for specifying clocks for synthesis, and how WAIT ON can be used to modify the sensitivity list I How passive processes can be used to perform error checking and other tasks across a number of architectures by existing in an ENTITY statement The next chapter focuses on all of the different data types of VHDL that can be used in models
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