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RETURN Z ; END CASE; END convert4val; FUNCTION convert4value(S : fourvalue) RETURN fourval IS BEGIN CASE S IS WHEN X => RETURN X; WHEN 0 => RETURN L; WHEN 1 => RETURN H; WHEN Z => RETURN Z; END CASE; END convert4value; END reg; ARCHITECTURE structure OF reg IS COMPONENT dff PORT(d, clk, clr : IN fourvalue; q : OUT fourvalue); END COMPONENT; BEGIN U1 : dff PORT MAP(convert4val(a(0)), convert4val(clk), convert4val(clr), convert4value(q) => q(0)); U2 : dff PORT MAP(convert4val(a(1)), convert4val(clk), convert4val(clr), convert4value(q) => q(1)); U3 : dff PORT MAP(convert4val(a(2)), convert4val(clk), convert4val(clr), convert4value(q) => q(2)); U4 : dff PORT MAP(convert4val(a(3)), convert4val(clk), convert4val(clr), convert4value(q) => q(3)); END structure;
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This example is a 4-bit register built out of flip-flops The type used in the entity declaration for the register is a vector of type fourval However, the flip-flops being instantiated have ports that are of type fourvalue A type mismatch error is generated if the ports of entity register are mapped
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directly to the component ports A conversion function is needed to convert between the two value systems If the ports are all of mode IN, then only one conversion is needed to map from the containing entity type to the contained entity type In this example, if all of the ports were of mode input, then only function convert4val would be required If the component has output ports as well, then the output values of the contained entity need to be converted back to the containing entity type In this example, the q port of component dff is an output port The type of the output values is fourvalue These values cannot be mapped to the type fourval ports of entity xregister Function convert4value converts from a fourvalue type to a fourval type Applying this function on the output ports allows the port mapping to occur There are four component instantiations that use these conversion functions: components U1 through U4 Notice that the input ports use the convert4val conversion function; the output ports use the convert4value conversion function Using the named association form of mapping for component instantiation, U1 would look like this:
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U1: dff PORT MAP ( d => convert4val( clk => convert4val( clr => convert4val( convert4value(q) =>
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a(0) ), clk ), clr ), q(0) );
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What this notation shows is that, for the input ports, the conversion functions are applied to the appropriate input signals (ports) before being mapped to the dff ports, and the output port value is converted with the conversion function before being mapped to the output port q(0) Conversion functions free the designer from generating a lot of temporary signals or variables to perform the conversion The following example shows another method for performing conversion functions:
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temp1 <= convert4val( a(0) ); temp2 <= convert4val( clk ); temp3 <= convert4val( clr ); U1: dff dlk => clk => clr => qlk => PORT MAP ( temp1, temp2, temp3, temp4); convert4value(temp4);
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q(0) <=
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Subprograms and Packages
This method is much more verbose, requiring an intermediate temporary signal for each port of the component being mapped This clearly is not the preferred method If a port is of mode INOUT, conversion functions cannot be used with positional notation The ports must use named association because two conversion functions must be associated with each inout port One conversion function is used for the input part of the inout port, and the other is used for the output part of the inout port In the following example, two bidirectional transfer devices are contained in an entity called trans2:
PACKAGE my_pack IS TYPE nineval IS (Z0, Z1, ZX, R0, R1, RX, F0, F1, FX); TYPE nvector2 IS ARRAY(0 TO 1) OF nineval; TYPE fourstate IS (X, L, H, Z); FUNCTION convert4state(a : fourstate) RETURN nineval; FUNCTION convert9val(a : nineval) RETURN fourstate; END my_pack; PACKAGE body my_pack IS FUNCTION convert4state(a : fourstate) RETURN nineval IS BEGIN CASE a IS WHEN X => RETURN FX; WHEN L => RETURN F0; WHEN H => RETURN F1; WHEN Z => RETURN ZX; END CASE; END convert4state; FUNCTION convert9val(a : nineval) RETURN fourstate IS BEGIN CASE a IS WHEN Z0 => RETURN Z; WHEN Z1 =>
RETURN Z; WHEN ZX => RETURN Z; WHEN R0 => RETURN L; WHEN R1 => RETURN H; WHEN RX => RETURN X; WHEN F0 => RETURN L; WHEN F1 => RETURN H; WHEN FX => RETURN X; END CASE; END convert9val; END my_pack; USE WORKmy_packALL; ENTITY trans2 IS PORT( a, b : INOUT nvector2; PORT( enable : IN nineval); END trans2; ARCHITECTURE struct OF trans2 IS COMPONENT trans PORT( x1, x2 : INOUT fourstate; PORT( en : IN fourstate); END COMPONENT; BEGIN U1 : trans PORT MAP( convert4state(x1) => convert9val(a(0)), convert4state(x2) => convert9val(b(0)), en => convert9val(enable) ); U2 : trans PORT MAP( convert4state(x1) => convert9val(a(1)), convert4state(x2) => convert9val(b(1)), en => convert9val(enable) ); END struct;
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