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FUNCTION int_to_st16(s : INTEGER) RETURN st16 IS VARIABLE result : st16; VARIABLE digit : INTEGER := 2**15; VARIABLE local : INTEGER; BEGIN local : = s; FOR i IN 15 DOWNTO 0 LOOP IF local/digit >>= 1 THEN result(i) := 1 ; local := local - digit; ELSE result(i) := 0 ; END IF; digit := digit/2; END LOOP; RETURN result; END int_to_st16; FUNCTION add(a, b: IN st16) RETURN st16 IS VARIABLE result : INTEGER; BEGIN result := vect_to_int(a) + vect_to_int(b); RETURN int_to_st16(result); END add; FUNCTION sub(a, b: IN st16) RETURN st16 IS VARIABLE result : INTEGER; BEGIN result := vect_to_int(a) - vect_to_int(b); RETURN int_to_st16(result); END sub; END math;
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The package declaration declares a type st16 and two functions, add and sub, that work with this type The package body has function bodies for function declarations add and sub and also includes two functions that are only used in the package body These functions are int_to_st16 and vect_to_int These functions are not visible outside of the package body To make these functions visible, a function declaration would need to be added to the package declaration, for each function
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Subprograms and Packages
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Functions vect_to_int and int_to_st16 must be declared ahead of function add to compile correctly All functions must be declared before they are used to compile correctly
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SUMMARY
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In this chapter, we discussed the different kinds of subprograms and some of the uses for them Specifically, we covered the following: I How subprograms consist of functions and procedures Functions have only input parameters and a single return value; procedures can have any number of in, out, and inout parameters I How functions can be used as conversion functions to convert from one type to another I How functions can be used as resolution functions to calculate the proper value on a multiple-driven network I How procedures are considered statements; functions are usually part of an expression Procedures can exist alone; functions are usually called as part of a statement I How packages are used to encapsulate information that is to be shared among multiple design units I How packages consist of a package declaration in which all of the type, subprogram, and other declarations exist and a package body in which subprogram bodies and deferred constants exist In the next chapter, we discuss how attributes can make some descriptions easier to read and more compact
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CHAPTER
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Predefined Attributes
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This chapter discusses VHDL predefined attributes and the way that concise readable models can be written using attributes Predefined attributes are data that can be obtained from blocks, signals, and types or subtypes The data obtained falls into one of the following categories shown: I Value kind A simple value is returned I Function kind A function call is performed to return a value I Signal kind A new signal is created whose value is derived from another signal I Type kind A type mark is returned I Range kind A range value is returned
Six
Predefined attributes have a number of very important applications Attributes can be used to detect clock edges, perform timing checks in concert with ASSERT statements, return range information about unconstrained types, and much more All of these applications are examined in this chapter First, we discuss each of the predefined attribute kinds and the ways that these attributes can be applied to modeling
Value Kind Attributes
Value attributes are used to return a particular value about an array of a type, a block, or a type in general Value attributes can be used to return the length of an array or the lowest bound of a type Value attributes can be further broken down into three subclasses: I Value type attributes, which return the bounds of a type I Value array attributes, which return the length of an array I Value block attributes, which return block information
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