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16-bit counter The architectures specify a synchronous counter with a synchronous load and clear All operations for the device occur with respect to the clock Each of the two configurations for the entity specifies a different architecture for the counter entity Let s examine the first configuration in more detail The configuration design unit begins with the keyword CONFIGURATION and is followed by the name of the configuration In this example, the name of the configuration is small_count The keyword OF precedes the name of the entity BEGIN configured (counter) The next line of the configuration starts the block configuration section The keyword FOR is followed by a name of the architecture to use for the entity being configured or the name of the block of the architecture that will be configured Any component or block configuration information then exists between the FOR ARCHITECTURE clause and the matching END FOR In this architecture, there are no blocks or components to configure; therefore, the block configuration area from the FOR clause to the END FOR clause is empty, and the default is used The configuration is called the default configuration, because the default is used for all objects in the configuration The first configuration is called small_count and binds architecture count_255 with entity counter to form a simulatable object The second configuration binds architecture count_64k with entity counter and forms a simulatable object called big_count
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In this section, we discuss how architectures that contain instantiated components can be configured Architectures that contain other components are called structural architectures These components are configured through component configuration statements Let s first look at some very simple examples of component configurations, and then at some progressively more complex examples The first example is a simple 2 to 4 decoder device Figure 7-1 shows the symbol for the decoder, and Figure 7-2 shows the schematic The components used in the design are defined using the VHDL description shown here:
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LIBRARY IEEE; USE IEEEstd_logic_1164ALL;
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Figure 7-1 Symbol for Decoder Example
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ENTITY inv IS PORT( a : IN std_logic; PORT( b : OUT std_logic); END inv; ARCHITECTURE behave OF inv IS BEGIN b <= NOT(a) AFTER 5 ns; END behave; CONFIGURATION invcon OF inv IS FOR behave END FOR; END invcon; LIBRARY IEEE; USE IEEEstd_logic_1164ALL; ENTITY and3 IS PORT( a1, a2, a3 : IN std_logic; PORT( o1 : OUT std_logic); END and3; ARCHITECTURE behave OF and3 IS BEGIN o1 <= a1 AND a2 AND a3 AFTER 5 ns; END behave; CONFIGURATION and3con OF and3 IS FOR behave END FOR; END and3con;
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Next, the entity and architecture for decode are shown:
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LIBRARY IEEE; USE IEEEstd_logic_1164ALL; ENTITY decode IS PORT( a, b, en : IN std_logic; PORT( q0, q1, q2, q3 : OUT std_logic); END decode;
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Figure 7-2 Gate Level Schematic for Decoder
nota
A notb
Q2 B
ARCHITECTURE structural OF decode IS COMPONENT inv PORT( a : IN std_logic; PORT( b : OUT std_logic); END COMPONENT; COMPONENT and3 PORT( a1, a2, a3 : IN std_logic; PORT( o1 : OUT std_logic); END COMPONENT; SIGNAL nota, notb : std_logic; BEGIN I1 : inv PORT MAP(a, nota); I2 : inv PORT MAP(b, notb); A1 : and3 PORT MAP(nota, en, notb, Q0); A2 : and3 PORT MAP(a, en, notb, Q1); A3 : and3
Configurations
PORT MAP(nota, en, b, Q2); A4 : and3 PORT MAP(a, en, b, Q3); END structural;
When all of the entities and architectures have been compiled into the working library, the circuit can be simulated The simulator uses the last compiled architecture to build the executable design for the simulator because it is the default Using the last compiled architecture for an entity to build the simulator works fine in a typical system, until more than one architecture exists for an entity Then it can become confusing as to which architecture was compiled last A better method is to specify exactly which architecture to use for each entity The component configuration binds architectures to entities Two different styles can be used for writing a component configuration for an entity The lower-level configuration style specifies lowerlevel configurations for each component, and the entity-architecture style specifies entity-architecture pairs for each component The word style is used to describe these two different configurations because there is no hard-and-fast rule about how to use them Lower-level configurations can be mixed with entity-architecture pairs, creating a mixed-style configuration
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