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Two of these can be connected with the entity architecture shown below to form a structural representation of the 3-input AND gate
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LIBRARY IEEE; USE IEEEstd_logic_1164ALL; ENTITY struc_and3 IS PORT( I1, I2, I3 : IN std_logic; PORT( O1 : OUT std_logic); END struc_and3; ARCHITECTURE structural OF struc_and3 IS COMPONENT and2 PORT( a, b : in std logic; c : out std logic ); END COMPONENT; SIGNAL s1, s2 : std_logic; BEGIN X1 : and2 PORT MAP( a => I1, b => I2, c => s1 ); X2 : and2 PORT MAP( a => I3, b => s1, c => O1 ); END structural;
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This architecture can then be configured with the following configuration:
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CONFIGURATION and3strc con OF struc and3 IS FOR structural FOR X1 : and2 USE CONFIGURATION WORKand2con; END FOR; FOR X2 : and2 USE CONFIGURATION WORKand2con; END FOR; END FOR; END and3strc con;
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Now, configuration decode_map_con of entity decode, described earlier, can be modified as follows:
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CONFIGURATION decode_map_con OF decode IS FOR structural FOR ALL : inv USE ENTITY WORKinv(behave); END FOR; FOR A1 : and3 USE ENTITY WORKstruc and3 (structural) PORT MAP ( I1 => a1, I2 => a2, I3 => a3, o1 => O1; END FOR; FOR OTHERS : and3 USE ENTITY WORKand3(behave); END FOR; END FOR; END decode_map_con;
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This configuration maps the first inverter, 3 input AND gate, A1, to entity struc_3, and other 3 input AND gates, A2 A4, to the behavioral entity, and3 Also the I1, I2, I3 and O1 ports of struc_and3 are mapped to ports a1, a2, a3 and o2 of the component declaration for component and3
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Generics in Configurations
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Generics are parameters that are used to pass information into entities Typical applications include passing in a generic value for the rise and fall delay of output signals of the entity Other applications include passing in temperature, voltage, and loading to calculate delay values in the model (Modeling efficiency delay calculations should be done prior to simulation and the calculated delay values can then be passed back into the model through generics) A description of generics can be found in 3, Sequential Processing This section concentrates on how configurations can be used to specify the value of generics Generics can be declared in entities, but can have a value specified in a number of places, as listed in the following: I A default value can be specified in the generic declaration I A value can be mapped in the architecture, in the component instantiation I A default value can be specified in the component declaration I A value can be mapped in the configuration for the component Default values specified in the generic declaration, or the component declaration, can be overridden by mapped values in the architecture or
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configuration sections If no overriding values are present, the default values are used; but if a value is mapped to the generic with a generic map, the default value is overridden To see an example of this, let s modify the decoder example, used previously in this chapter, to include two generics The first specifies a timing mode to run the simulation, and the second is a composite type containing the delay values for the device These two types are declared in the package p_time_pack, as shown in the following:
LIBRARY IEEE; USE IEEEstd_logic_1164ALL; PACKAGE p_time_pack IS TYPE t_time_mode IS (minimum, typical, maximum); TYPE t_rise_fall IS RECORD rise : TIME; fall : TIME; END RECORD; TYPE t_time_rec IS ARRAY(t_time_mode LOW TO t_time_mode HIGH) OF t_rise_fall; FUNCTION calc_delay(newstate : IN std_logic; mode : IN t_time_mode; delay_tab : IN t_time_rec ) return time; END p_time_pack; PACKAGE BODY p_time_pack IS FUNCTION calc_delay(newstate : IN std_logic; mode : IN t_time_mode; delay_tab : IN t_time_rec ) return time IS BEGIN CASE f_state(newstate) IS WHEN 0 => RETURN delay_tab(mode)fall; WHEN 1 => RETURN delay_tab(mode)rise; WHEN X => IF (delay_tab(mode)rise <= delay_tab(mode)fall) THEN RETURN delay_tab(mode)rise; ELSE RETURN delay_tab(mode)fall; END IF; END CASE; END calc_delay; END p_time_pack;
This package declares types t_time_mode and t_time_rec, which are used for the generics of the inverter and 3-input AND gates It also includes
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