barcode scanner c# code project Board-Socket-Chip Analogy in Visual C#

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Board-Socket-Chip Analogy
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A good analogy for describing how entity declarations, architectures, component declarations, and configuration specifications all interact is the
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Figure 7-3 Configuration Generic Table
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Declaration Entity D D D N N X X X D/N D/N Component D N N D D D/N D/N D/N X X A X A A A Instance A A
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Mapping Configuration
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Generic Values Same I I Other E E E M M
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A A 1 2 2 3 A A X 4 5
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Figure 7-4 Configuration Generic Table Translations
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Declarations / Mapping D N X A Declared, with default value Declared, with no default value Not Declared Actual Mapped
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Seven
Errors / Warnings 1 2 3 4 5 Can only map generic in configuration if declared in the entity Generic declared in component but not in entity, hence it is not used Can only map generic in component instance if declared in component declarations Can t map a generic in the component instance and the configuration Must map at least one generic to get the default value for other generics
Generic Values E M I C Default taken from entity Default taken from configuration Actual taken from component instance Actual taken from configuration
board-socket-chip analogy (This analogy was originally presented to me by Dr Alec Stanculescu) In this analogy, the architecture of the top-level entity represents the board being modeled The component instance represents a socket on the board, and the lower-level entity being instantiated in the architecture represents the chip This analogy helps describe how the ports and generics are mapped at each level At the board (architecture) level component socket pins are interconnected with signals The chip pins are then connected to socket pins when the chip is plugged into the socket Following is an example of how this works:
LIBRARY IEEE; USE IEEEstd_logic_1164ALL;
Configurations
ENTITY board IS GENERIC (qdelay, qbdelay : time); PORT( clk, reset, data_in : IN std_logic; PORT( data_out : OUT std_logic); END board; ARCHITECTURE structural OF board IS COMPONENT dff GENERIC( g1, g2 : time); PORT( p1, p2, p3, p4 : IN std_logic; p5, p6 : OUT std_logic); END COMPONENT; SIGNAL ground : std_logic := 1 ; SIGNAL int1, nc : std_logic; BEGIN U1 : dff GENERIC MAP( g1 => qdelay, GENERIC MAP( g2 => qbdelay) PORT MAP( p1 => clk, PORT MAP( p2 => data_in, PORT MAP( p3 => reset, PORT MAP( p4 => ground, PORT MAP( p5 => int1, PORT MAP( p6 => nc); U2 : dff GENERIC MAP( g1 GENERIC MAP( g2 PORT MAP( p1 => PORT MAP( p2 => PORT MAP( p3 => PORT MAP( p4 => PORT MAP( p5 => PORT MAP( p6 => END structural;
=> qdelay, => qbdelay) clk, int1, reset, ground, data_out, nc);
The entity and architecture shown are a simple 2-bit shift register made from two D flip-flop (DFF) component instantiations This example, though relatively simple, shows how ports and generics are mapped at different levels The component instance for component DFF in the architecture statement part acts like a socket in the architecture for the board When a component instance is placed in the architecture, signals are used to connect the component to the board, which is the architecture The actual chip is not connected to the socket until a configuration is specified for the board entity If all of the names of the socket ports and generics match the names of the actual entity being used, then no mapping is needed The default mapping connects the chip to the socket If the names are different, or the number of ports are not the same, for the component instanti-
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ation and the actual entity, then a mapping between the socket (component instantiation) and the chip (actual entity) is needed The actual chip to be mapped is described by the entity and architecture shown here:
LIBRARY IEEE; USE IEEEstd_logic_1164ALL; ENTITY dff IS GENERIC( q_out, qb_out : time); PORT( preset, clear, din, PORT( clock : IN std_logic; PORT( q, qb : OUT std_logic); END dff; ARCHITECTURE behave OF dff IS BEGIN dff_proc : PROCESS(preset, clear, clock) VARIABLE int_q : std_logic; BEGIN IF preset = 0 and clear = 0 THEN IF (clock EVENT) AND (clock = 1 ) THEN int_q := din; END IF; ELSIF preset = 1 AND clear = 0 THEN int_q := 1 ; ELSIF clear = 1 AND preset = 0 THEN int_q := 0 ; ELSE int_q := X ; END IF; q <= int_q after q_out; int_q := not(int_q); qb <= int_q after qb_out; END PROCESS dff_proc; END behave;
The names of the ports and generics are completely different than the component declaration; therefore, mapping is required Following is a configuration that places the actual chip in the socket (maps the ports and generics):
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