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make the source being assigned to the signal Now, whenever the target signal type is changed, the source changes to match
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User-Defined Attributes
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VHDL user-defined attributes are a mechanism for attaching data to VHDL objects The data attached can be used during simulation or by another tool that reads the VHDL description Data such as the disk file name of the model, loading information, driving capability, resistance, capacitance, physical location, and so on can be attached to objects The type and value of the data is completely user-definable The value, when specified, is constant throughout the simulation User-defined attributes can behave similar to entity generic values, with one exception Generics are only legal on entities, but user-defined attributes can be assigned to the following list of objects: I Entity I Architecture I Configuration I Procedure I Function I Package I Type and Subtype I Constant I Signal I Variable I Component I Label To see how user-defined attributes operate, let s examine the following description:
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PACKAGE p_attr IS TYPE t_package_type IS ( leadless, TYPE t_package_type IS ( pin_grid, TYPE t_package_type IS ( dip); ATTRIBUTE package_type : t_package_type;
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ATTRIBUTE location : INTEGER; END p_attr; USE WORKp_attrALL; ENTITY board IS PORT( ); END board; ARCHITECTURE cpu_board OF board IS COMPONENT mc68040 GENERIC( ); PORT( ); END COMPONENT; SIGNAL a : INTEGER; SIGNAL b : t_package_type;
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ATTRIBUTE package_type OF mc68040 : COMPONENT IS pin_grid; ATTRIBUTE location OF mc68040 : COMPONENT IS 20; BEGIN a <= mc68040 location; -- returns 20 b <= mc68040 package_type; -- returns pin_grid END cpu_board;
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This is a very simple example of how attributes can be attached to objects Much more complicated types and attributes can be created What this example shows is a code fragment of a CPU board design in which the package type and location information are specified as attributes of the single microprocessor used in the design The package_type attribute is used to hold the kind of packaging used for the microprocessor Attributes that have values specified do not have to be used in the simulation Other tools such as physical layout tools or fault simulation can make use of attributes that a logic simulator cannot In this example, a physical layout tool could read the package type information from the package_type attribute and, based on the value assigned to the attribute, fill in the value for the location attribute
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The package p_attr defines the type used for one of the attributes and contains the attribute declarations for two attributes The attribute declarations make the name and type of the attribute visible to any object for use if needed In the architecture cpu_board of entity board are the attribute specifications The attribute specification describes the attribute name to be used, the name of the object to which the attribute is attached, the object kind, and finally the value of the attribute To access the value of a user-defined attribute, use the same syntax for a predefined attribute In the signal assignment statements of architecture cpu_board, the attribute value is retrieved by specifying the name of the object, followed by a and the attribute name
Generate Statements
Generate statements give the designer the ability to create replicated structures, or select between multiple representations of a model Generate statements can contain IF-THEN and looping constructs, nested to any level, that create concurrent statements Typical applications include memory arrays, registers, and so on Another application is to emulate a conditional compilation mechanism found in other languages such as C Following is a simple example showing the basics of generate statements:
LIBRARY IEEE; USE IEEEstd_logic_1164ALL; ENTITY shift IS PORT( a, clk : IN std_logic; PORT( b : OUT std_logic); END shift; ARCHITECTURE gen_shift OF shift IS COMPONENT dff PORT( d, clk : IN std_logic; PORT( q : OUT std_logic); END COMPONENT; SIGNAL z : std_logic_vector( 0 TO 4 ); BEGIN z(0) <= a; g1 : FOR i IN 0 TO 3 GENERATE dffx : dff PORT MAP( z(i), clk, z(i + 1));
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