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END GENERATE; b <= z(4); END gen_shift;
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This example represents the behavior for a 4-bit shift register Port a is the input to the shift register, and port b is the output Port clk shifts the data from a to b Architecture gen_shift of entity shift contains two concurrent signal assignment statements and one GENERATE statement The signal assignment statements connect the internal signal z to input port a and output port b The generate statement in this example uses a FOR scheme to generate four DFF components The resultant schematic for this architecture is shown in Figure 8-1 The FOR in the generate statement acts exactly like the FOR loop sequential statement in that variable i need not be declared previously, i is not visible outside the generate statement, and i cannot be assigned inside the generate statement The result of the generate statement is functionally equivalent to the following architecture:
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ARCHITECTURE long_way_shift OF shift IS COMPONENT dff PORT( d, clk : IN std_logic; PORT( q : OUT std_logic); END COMPONENT; SIGNAL z : std_logic_vector( 0 TO 4 ); BEGIN z(0) <= a; dff1: dff2: dff3: dff4: dff dff dff dff PORT PORT PORT PORT MAP( MAP( MAP( MAP( z(0), z(1), z(2), z(3), clk, clk, clk, clk, z(1) z(2) z(3) z(4) ); ); ); );
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Figure 8-1 Schematic Representing Generate Statement
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DFFX(0) Z(0) A D CLK Q Z(1)
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DFFX(1) Z(2) D CLK Q
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DFFX(2) Z(3) D CLK Q
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DFFX(3) Z(4) D CLK Q B
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b <= z(4); END long_way_shift;
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Eight
The difference between the two architectures is that architecture gen_shift could be specified with generic parameters such that different-sized shift registers could be generated based on the value of the generic parameters Architecture long_way_shift is fixed in size and cannot be changed
Irregular Generate Statement
The last example showed how a regular structure could be generated, but in practice most structures are not completely regular Most regular structures have irregularities at the edges This is shown by Figure 8-2 In the last example, the irregularities were handled by the two concurrent signal assignment statements Following is another way to handle the irregularities:
LIBRARY IEEE; USE IEEEstd_logic_1164ALL; ENTITY shift IS GENERIC ( len : INTEGER); PORT( a, clk : IN std_logic; PORT( b : OUT std_logic); END shift; ARCHITECTURE if_shift OF shift IS COMPONENT dff PORT( d, clk : IN std_logic; PORT( q : OUT std_logic); END COMPONENT; SIGNAL z : std_logic_vector( 1 TO (len -1) ); BEGIN g1 : FOR i IN 0 TO (len -1) GENERATE
Figure 8-2 Irregular Generate Statement Representation
DFFX(0) Z(1) A D CLK Q
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IF i = 0 GENERATE dffx : dff PORT MAP( a, clk, z(i + 1)); END GENERATE; IF i = (len -1) GENERATE dffx : PORT MAP( z(i), clk, b ); END GENERATE; IF (i > 0) AND i < (len -1) GENERATE dffx : PORT MAP( z(i), clk, Z(i + 1) ); END GENERATE; END GENERATE; END if_shift;
This example uses a shift register that has a configurable size Generic
len passed in specifies the length of the shift register (Generic len must be at least 2 for the shift register to work properly) Generic len is used in the specification of the length of signal array z This type of array is known
as a generically constrained array because the size of the array is specified through one or more generics The FOR clause of the generate also uses generic len to specify the maximum number of DFF components to be generated Notice that this generate statement uses the conditional form of the generate statement If the condition is true, the concurrent statements inside the generate statement are generated; otherwise, nothing is generated The first IF-THEN condition checks for the first flip-flop in the shift register If this is the first flip-flop, notice that the port map clause maps the input signal a directly to the flip-flop instead of through an intermediate signal The same is true of the next IF-THEN condition It checks for the last flip-flop of the shift register and maps the last output to output port b Any other flip-flops in the shift register are generated by the third conditional generate statement Following is another interesting example using the conditional generate statement:
PACKAGE gen_cond IS TYPE t_checks IS ( onn, off); END gen_cond; USE WORKgen_condALL; LIBRARY IEEE; USE IEEEstd_logic_1164ALL; ENTITY dff IS GENERIC( timing_checks : t_checks;
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