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SUMMARY
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In this chapter we discussed the following: I Overloading functions, arguments, operators to make VHDL models more readable I How aliases can be used to name sections of an object I How qualified expressions are used to direct conversion I How user-defined attributes can be used to add information to objects I How generate statements can be used to replicate entity instantiations I How TextIO is used to read and write text files This chapter showed some of the more esoteric features of VHDL This chapter concludes the discussion of VHDL features The next two chapters concentrate on the synthesis process and how to write VHDL for synthesis The next few chapters then guide the reader through a topdown description of a device
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CHAPTER
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Synthesis
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One of the best uses of VHDL today is to synthesize ASIC and FPGA devices This chapter and the next focus on how to write VHDL for synthesis Synthesis is an automatic method of converting a higher level of abstraction to a lower level of abstraction There are several synthesis tools available currently, including commercial as well as university-developed tools In this discussion, the examples use the commercially available Exemplar Logic Leonardo Sectrum synthesis tool The current synthesis tools available today convert Register Transfer Level (RTL) descriptions to gate level netlists These gate level netlists consist of interconnected gate level macro cells Models for the gate level cells are contained in technology libraries for each type of technology supported
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Figure 9-1 Gate Level Netlist Synthesis
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Technology Library
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Nine
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RTL Description Gate Level Netlists
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Synthesis
Constraints
These gate level netlists currently can be optimized for area, speed, testability, and so on The synthesis process is shown in Figure 9-1 The inputs to the synthesis process are an RTL (Register Transfer Level) VHDL description, circuit constraints and attributes for the design, and a technology library The synthesis process produces an optimized gate level netlist from all of these inputs In the next few sections, each of these inputs is described, and we discuss the synthesis process in more detail
Register Transfer Level Description
A register transfer level description is characterized by a style that specifies all of the registers in a design, and the combinational logic between This is shown by the register and cloud diagram in Figure 9-2 The registers are described either explicitly through component instantiation or implicitly through inference The registers are shown as the rectangular objects connected to the clock signal The combinational logic is described by logical equations, sequential control statements (CASE, IF then ELSE, and so on), subprograms, or through concurrent statements, which are represented by the cloud objects between registers
Synthesis
Register Register
Datain Combinational Logic Dataout
Figure 9-2 Register and Cloud Diagram
Clock
RTL descriptions are used for synchronous designs and describe the clock-by-clock behavior of the design Following is an example of an RTL description that uses component instantiation:
ENTITY datadelay IS PORT( clk, din, en : IN BIT; PORT( dout : OUT BIT); END datadelay; ARCHITECTURE synthesis OF datadelay IS COMPONENT dff PORT(clk, din : IN BIT; PORT(q,qb : OUT BIT); END COMPONENT; SIGNAL q1, q2, qb1, qb2 : BIT; BEGIN r1 : dff PORT MAP(clk, din, q1, qb1); r2 : dff PORT MAP(clk, q1, q2, qb2); dout <= q1 WHEN en = 1 ELSE q2; END synthesis;
This example is the circuit for a selectable data delay circuit The circuit delays the input signal din by 1 or 2 clocks depending on the value of en If en is a 1, then input din is delayed by 1 clock If en is a 0, input din is delayed by 2 clocks Figure 9-3 shows a schematic representation of this circuit The clock signal connects to the clk input of both flip-flops, while the din signal connects only to the first flip-flop The q output of the first flip-flop is then
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