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Figure 9-3 Register Transfer Level with Component Instances
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connected to the d input of the next flip-flop The selected signal assignment to signal dout forms a mux operation that selects between the two flip-flop outputs This example could be rewritten as follows using register inference:
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ENTITY datadelay IS PORT( clk, din, en : IN BIT; PORT( dout : OUT BIT); END datadelay; ARCHITECTURE inference OF datadelay IS SIGNAL q1, q2 : BIT; BEGIN reg_proc: PROCESS BEGIN WAIT UNTIL clk EVENT and clk = 1 ; q1 <= din; q2 <= q1; END PROCESS; dout <= q1 WHEN en = 1 ELSE q2;
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Synthesis
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END inference;
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In the first version, the registers are instantiated using component instantiation statements that instantiate r1 and r2 In this version, the dff components are not instantiated, but are inferred through the synthesis process Register inference is discussed more in 10, VHDL Synthesis Process reg_proc has a WAIT statement that is triggered by positive edges on the clock When the WAIT statement is triggered, signal q1 is assigned the value of din, and q2 is assigned the previous value of q1 This, in effect, creates two flip-flops One flip-flop for signal q1, and the other for signal q2 This is a register transfer level description because registers r1 and r2 from the first version form the registers, and the conditional signal assignment for port dout forms the combinational logic between registers In the second version, the inferred registers form the register description, while the conditional signal assignment still forms the combinational logic The advantage of the second description is that it is technology independent In the first description, actual flip-flop elements from the technology library were instantiated, thereby making the description technology dependent If the designer should decide to change technologies, all of the instances of the flip-flops would need to be changed to the flip-flops from the new technology In the second version of the design, the designer did not specify particular technology library components, and the synthesis tools are free to select flip-flops from whatever technology library the designer is currently using, as long as these flip-flops match the functionality required After synthesis, both of these descriptions produce a gate level description, as shown in Figure 9-4 Notice that the gate level description has two registers (FDSR1) with mux (Mux21S) logic controlling the output signal from each register Depending on the technology library selected and the constraints, the mux logic varies widely from and-or-invert gates to instantiated 2-input multiplexers Following is the netlist generated by the Exemplar Logic Leonardo Spectrum synthesis tool for the same design:
- -- Definition of - -- - - -
datadelay
Figure 9-4 A Gate Level Description
en q2 clk CP D q1 CP din D FDSR1 Q FDSR1 Q A B S
Nine
dout z dout
MUX21S
library IEEE, EXEMPLAR; use IEEESTD_LOGIC_1164all; use EXEMPLAREXEMPLAR_1164all; entity datadelay is port ( clk : IN std_logic ; din : IN std_logic ; en : IN std_logic ; dout : OUT std_logic) ; end datadelay ; architecture inference of datadelay is component FDSR1 port ( Q : OUT std_logic ; D : IN std_logic ; CP : IN std_logic) ; end component ; component MU21S port ( Z : OUT std_logic ; A : IN std_logic ; B : IN std_logic ; S : IN std_logic) ; end component ; signal q2, q1: std_logic ; begin q2_XMPLR : FDSR1 port map ( Q=>q2, D=>q1, CP=>clk); q1_XMPLR : FDSR1 port map ( Q=>q1, D=>din, CP=>clk); dout_XMPLR_XMPLR : MU21S port map ( Z=>dout, A=>q2, B=>q1, S=>en); end inference ;
Synthesis
The netlist matches the gate level generated schematic The netlist contains two instantiated flip-flops (FDSR1) and one instantiated 2-input multiplexer (Mux21S) This very simple example shows how RTL synthesis can be used to create technology-specific implementations from technology-independent VHDL descriptions In the next few sections, we examine much more complex examples But first, let s look at some of the ways to control how the synthesized design is created
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