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FOR U7 : orgate USE ENTITY WORKmyor(version1); END FOR; END FOR; END muxcon1;
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The function of the configuration statement is to spell out exactly which architecture to use for every component instance in the model This occurs in a hierarchical fashion The highest-level entity in the design needs to have the architecture to use specified, as well as any components instantiated in the design The preceding configuration statement reads as follows: This is a configuration named muxcon1 for entity mux Use architecture netlist as the architecture for the topmost entity, which is mux For the two component instances U1 and U2 of type inverter instantiated in the netlist architecture, use entity myinv, architecture version1 from the library called WORK For the component instances U3-U6 of type andgate, use entity myand, architecture version1 from library WORK For component instance U7 of type orgate use entity myor, architecture version1 from library WORK All of the entities now have architectures specified for them Entity mux has architecture netlist, and the other components have architectures named version1 specified
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Power of Configurations
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By compiling the entities, architectures, and the configuration specified earlier, you can create a simulatable model But what if you did not want to simulate at the gate level What if you really wanted to use architecture BEHAVE instead The power of the configuration is that you do not need to recompile your complete design; you only need to recompile the new configuration Following is an example configuration:
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CONFIGURATION muxcon2 OF mux IS FOR dataflow END FOR; END muxcon2;
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This is a configuration named muxcon2 for entity mux Use architecture dataflow for the topmost entity, which is mux By compiling this configuration, the architecture dataflow is selected for entity mux in this simulation This configuration is not necessary in standard VHDL, but gives the designer the freedom to specify exactly which architecture will be used for the entity The default architecture used for the entity is the last one compiled into the working library
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Introduction to VHDL
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In this chapter, we have had a basic introduction to VHDL and how it can be used to model the behavior of devices and designs The first example showed how a simple dataflow model in VDHL is specified The second example showed how a larger design can be made of smaller designs in this case a 4-input multiplexer was modeled using AND, OR and INVERTER gates The first example provided a structural view of VHDL The last example showed an algorithmic or behavioral view of the mux All these views of the mux successfully model the functionality of a mux and all can be simulated with a VHDL simulator Ultimately, however, a designer will want to use the model to facilitate building a piece of hardware The most common use of VHDL in actually building hardware today is through synthesis tools Therefore, the focus of the rest of the book is not only on the simulation of VHDL but also on the synthesis of VHDL
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CHAPTER
Behavioral Modeling
In 1, we discussed different modeling techniques and touched briefly on behavioral modeling In this chapter, we discuss behavioral modeling more thoroughly, as well as some of the issues relating to the simulation and synthesis of VHDL models
Two
Introduction to Behavioral Modeling
The signal assignment statement is the most basic form of behavioral modeling in VHDL Following is an example:
a <= b;
This statement is read as follows: a gets the value of b The effect of this statement is that the current value of signal b is assigned to signal a This statement is executed whenever signal b changes value Signal b is in the sensitivity list of this statement Whenever a signal in the sensitivity list of a signal assignment statement changes value, the signal assignment statement is executed If the result of the execution is a new value that is different from the current value of the signal, then an event is scheduled for the target signal If the result of the execution is the same value, then no event is scheduled but a transaction is still generated (transactions are discussed in 3, Sequential Processing ) A transaction is always generated when a model is evaluated, but only signal value changes cause events to be scheduled The next example shows how to introduce a nonzero delay value for the assignment:
a <= b after 10 ns;
This statement is read as follows: a gets the value of b when 10 nanoseconds of time have elapsed Both of the preceding statements are concurrent signal assignment statements Both statements are sensitive to changes in the value of signal b Whenever b changes value, these statements execute and new values are assigned to signal a Using a concurrent signal assignment statement, a simple AND gate can be modeled, as follows:
ENTITY and2 IS PORT ( a, b : IN BIT; PORT ( c : OUT BIT ); END and2; ARCHITECTURE and2_behav OF and2 IS BEGIN c <= a AND b AFTER 5 ns;
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