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gte <= 1 ; END IF; WHEN less_equal => IF (a > b) THEN lte <= 1 ; END IF; END CASE; END PROCESS; END synth;
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Notice that, in this example, the equations of the inputs and outputs are harder to write because of the comparison operators It is still possible to do, but is much less readable than the case statement shown earlier When synthesizing a design, the complexity of the design is related to the complexity of the equations that describe the design function Typically, the more complex the equations, the more complex the design created There are exceptions to this rule, especially when the equations reduce to nothing A sample synthesized output from the preceding description is shown in Figure 10-5 The inputs are shown on the left of the schematic diagram, and the outputs are shown in the lower right of the schematic The equations for the comparison operators have all been shared and combined together to produce an optimal design This design is a very small number of gates for the operation performed There are still a number of cases where hand design can create smaller designs, but in most cases today the results of synthesis are very good; and you get the added benefit of using a higher level design language for easier maintainability and a shorter design cycle
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Simple Sequential Statements
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Let s take a closer look at an example that we already discussed in the last chapter This is the inferred D flip-flop Inferred flip-flops are created by WAIT statements or IF THEN ELSE statements, which are surrounded by sensitivities to a clock By detecting clock edges, the synthesis tool can locate where to insert flip-flops so that the design that is ultimately built behaves as the simulation predicts Following is an example of a simple sequential design using a WAIT statement:
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LIBRARY IEEE; USE IEEEstd_logic_1164ALL; ENTITY dff IS
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Figure 10-5 A Sample Synthesized Output
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Ten
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PORT( clock, din : IN std_logic; PORT( dout : OUT std_logic); END dff; ARCHITECTURE synth OF dff IS BEGIN PROCESS BEGIN WAIT UNTIL ((clock EVENT) AND (clock = 1 )); dout <= din; END PROCESS; END synth;
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VHDL Synthesis
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The description contains a synthesizable entity and architecture representing a D flip-flop The entity contains the clock, din, and dout ports needed for a D flip-flop, while the architecture contains a single process statement with a single WAIT statement When the clock signal has a rising edge occur, the contents of din are assigned to dout Effectively, this is how a D flip-flop operates The synthesized output of this design matches the functionality of the RTL description It is very important for the synthesis and simulation results to agree Otherwise, the resulting synthesized design may not work as planned Part of the synthesis methodology should require that a final gate level simulation of the design is executed to verify that the gate level functionality is correct (We perform this step in an example later on) The output of the Leonardo synthesis tool is shown in Figure 10-6 As expected, the output of the synthesis tool produced a single D flipflop The synthesis tool connected the ports of the entity to the proper ports of actual FPGA library macro so that the device works as expected in the design
Asynchronous Reset
In a number of instances, D flip-flops are required to have an asynchronous reset capability The previous D flip-flop did not have this capability How would we generate a D flip-flop with an asynchronous reset Remember the simulation and synthesis results must agree Following is one way to accomplish this:
LIBRARY IEEE; USE IEEEstd_logic_1164ALL; ENTITY dff_asynch IS
Figure 10-6 The Output of the Leonardo Synthesis Tool
din clock
dout
PORT( clock, reset, din : IN std_logic; PORT( dout : OUT std_logic); END dff_asynch;
Ten
ARCHITECTURE synth OF dff_asynch IS BEGIN PROCESS(reset, clock) BEGIN IF (reset = 1 ) THEN dout <= 0 ; ELSEIF (clock EVENT) AND (clock = 1 ) THEN dout <= din; END IF; END PROCESS; END synth;
The ENTITY statement now has an extra input, the reset port, which is used to asynchronously reset the D flip-flop Notice that reset and clock are in the process sensitivity list and cause the process to be evaluated If an event occurs on signals clock or reset, the statements inside the process are executed First, signal reset is tested to see if it has an active value ( 1 ) If active, the output of the flip-flop is reset to 0 If reset is not active ( 0 ), then the clock signal is tested for a rising edge If signal clock has a rising edge, then input din is assigned as the new flip-flop output The fact that the reset signal is tested first in the IF statement gives the reset signal a higher priority than the clock signal Also, because the reset signal is tested outside of the test for a clock edge, the reset signal is asynchronous to the clock The Leonardo synthesis tool produces a D flip-flop with an asynchronous reset input, as shown in Figure 10-7 The resulting design has an extra inverter (IVP component) in the circuit because the only flip-flop macro that would match the functionality required had a reset input that was active low
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