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counter It is the process that is clocked by the clock and transfers the new calculated output count_val to the current output dout The other process contains a single IF statement that determines whether the counter is being loaded, cleared, or is counting up A sample synthesized output is shown in Figure 10-9 In this example, the generated results are as expected The left side of the schematic shows the inputs to the counter; the right side of the schematic has the counter output Notice that the design contains four flip-flops (FDSR1), exactly as specified Also, notice that the logic generated for the counter is very small This design was optimized for area; thus, the number of levels of logic are probably higher than a design optimized for speed
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Four-Bit Shifter
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Another sequential example is a 4-bit shifter This shifter can be loaded with a value and can be shifted left or right one bit at a time Following is the model for the shifter:
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LIBRARY IEEE; USE IEEEstd_logic_1164ALL; PACKAGE shift_types IS SUBTYPE bit4 IS std_logic_vector(3 downto 0); END shift_types;
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USE WORKshift_typesALL; LIBRARY IEEE; USE IEEEstd_logic_1164ALL; ENTITY shifter IS PORT( din : IN bit4; clk, load, left_right : IN std_logic; dout : INOUT bit4); END shifter; ARCHITECTURE synth OF shifter IS SIGNAL shift_val : bit4; BEGIN nxt: PROCESS(load, left_right, din, dout) BEGIN IF (load = 1 ) THEN shift_val <= din; ELSEIF (left_right = 0 ) THEN shift_val(2 downto 0) <= dout(3 downto 1); shift_val(3) <= 0 ; ELSE shift_val(3 downto 1) <= dout(2 downto 0);
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VHDL Synthesis
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Figure 10-9 A Sample Synthesized Output
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shift_val(0) <= 0 ; END IF; END PROCESS; current: PROCESS BEGIN WAIT UNTIL clk EVENT AND clk = 1 ; dout <= shift_val; END PROCESS; END synth;
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The 4-bit type used for the input and output of the shifter is declared in package shift_types This package is used by entity shifter to declare ports din and dout Ports clk, load, and left_right are std_logic signals used to control the functions of the shifter
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Ten
The architecture is organized similarly to the last example, with two processes used to describe the functionality of the architecture One process keeps track of the current value of the shifter, and the other calculates the next value based on the last value and the control inputs Process current is used to keep track of the current value of the shifter It is a process that has a single WAIT statement and a single signal assignment statement When the clk signal has a rising edge occur, the signal assignment statement is activated and the next calculated value of the shifter (shift_val) is written to the signal that holds the current state of the shifter (dout) Process nxt is used to calculate the next value of shift_val to be written into dout Load is the highest priority input and, if equal to 1 , causes shift_val to receive the value of din Otherwise, signal left_right is tested to see if the shifter is shifting left or right Because this shifter does not contain a carryin or carryout, 0 values are written into the bits whose value has been shifted over (A good exercise is to write a shifter that contains a carryin and carryout) The synthesis tool produces a schematic for this input description as shown in Figure 10-10 By counting the flip-flops (FDSR1) on the page, it can be seen that this is indeed a 4-bit shifter
State Machine Example
The next example is a simple state machine used to control a voicemail system (This example does not represent any real system in use and is necessarily simple to make it easier to fit in the book) The voicemail controller allows the user to send messages, review messages, save messages, and erase messages A state diagram showing the possible state transitions is shown in Figure 10-11 The normal starting state is state main From main, the user can select whether to review messages or send messages To get to the Review menu, the user presses the 1 key on the touch-tone phone To select the Send Message menu, the user presses the 2 key on the touch-tone phone After the user has selected either of these options, further menu options allow the user to perform other functions such as Save and Erase For instance, if the user first selects the Review menu by pressing key 1, then pressing key 2 allows the user to save a reviewed message when reviewing is complete Following is the VHDL description for the voicemail controller:
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