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Now that microprocessors are available, more convenient gating periods are used In the second method, a timed gating period of, say, 1 second, 1 minute, or 1 hour is used, and a calculation of BER is made from the accumulated totals The advantage of this method is that it provides results that are compatible with the error-performance criteria discussed subsequently The third method determines the gating period by counting sufficient errors (typically 100 or more) for statistically reliable results Again, the processor calculates BER from the accumulated totals This method can lead to very long gating periods with low BER values For example, a system running at 100 Mbps with a BER of 10-12 would take nearly 12 days to accumulate 100 errors The most commonly used method is the second, which calculates BER after a fixed, repetitive gating period In this case, the variance in the result will continuously change, so it is normal to give some kind of warning if the variance exceeds generally acceptable levels The most widely accepted level is 10 percent, ie, an error count of at least 100 errors In practical digital transmission systems, particularly those using radio propagation, the BER can vary substantially over time In this case, the long-term mean value provides only part of the story Communications engineers also are interested in the percentage of time the system under test is unacceptably degraded This is called error analysis or error performance, which is discussed in section 2633
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2631 Test patterns
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As alluded to previously, the choice of test pattern is usually made between a PRBS (to simulate traffic) and specific word patterns (to examine pattern-dependent tendencies or critical timing effects) With a PRBS, the choice of binary sequence and the resulting spectral and run properties are important These properties may be summarized:
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Sequence length, in bits Shift register feedback configuration defining binary run properties Spectral line spacing, which depends on bit rate (see Figure 265)
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Figure 265 This is the ideal spectrum of a binary nonreturn to zero (NRZ) PRBS It has a line spectrum in which the line spacing is determined by the bit rate (fb) and the sequence length 2n 1 (see Table 261)
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TABLE 261 Relationship Between Sequence Length and Bit Rate with Corresponding Spectral Line Spacing for Some Standard Telecommunications Transmission Rates
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Bit rate (fb), kbps 1,544 2,048 34,368 44,736 139,264
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Sequence Length (n) 215 1 bits 215 223 1 bits 1 bits
Polynomial D15 + D14 + 1 = 0 D15 + D14 + 1 = 0 D23 + D18 + 1 = 0 D15 + D14 + 1 = 0 D23 + D18 + 1 = 0
Spectral Line (fb/n), Hz 471 625 41 13653 166
215 1 bits 223 1 bits
Figure 266 The PRBS pattern generator consists of a shift register with feedback taps
connected to an exclusive-OR gate The output of the shift register may be inverted to create a signal with the maximum run of 0s The polynomial that defines the PRBS determines where the feedback connections are made The expression for this diagram would be Dn + Dn 1 + 1 = 0
PRBS patterns have been standardized by the ITU-T for testing digital transmission systems (Recommendations O151, O152, and O153) The most commonly used patterns in digital transmission testing are summarized in Table 261 Table 261 shows some examples of sequences specified by the ITU-T for several standard telecommunications bit rates Note that the longer sequences give closer spectral line spacing; typically, the higher the operating bit rate, the longer is the required sequence to simulate real data traffic For tests in the Gbps range, some test sets now provide a 231 1 sequence length Adequate (ie, close enough) spectral line spacing is important when testing systems containing relatively narrowband (high-Q) clock timing recovery circuits in order to see the jitter contribution of these and its effect on error performance The shift register configuration is defined by a polynomial of the type shown in Table 261 The letter D stands for delay; the expression D15 + D14 + 1 = 0, for example, means that the outputs of the fifteenth and fourteenth stages of the shift register are connected to an exclusive-OR gate, the output of which drives the first shift register stage, as shown in Figure 266 This basic circuit arrangement generates a sequence with a maximum run of 1s rather than 0s It is common to invert the output to generate a maximum run of 0s, since this may create more stringent conditions for a clock recovery circuit The simple three-stage PRBS generator shown in Figure 267 with the truth table helps to explain the operation of the feedback shift register This has a sequence length of 23 1, or 7 bits
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