Bit Error Rate Measurements and Error Performance Analysis 600 Network Test Instrumentation in Software

Printing Code 128 Code Set C in Software Bit Error Rate Measurements and Error Performance Analysis 600 Network Test Instrumentation

Figure 269 An example of stored word patterns in a BER test set The list in-

cludes some simple PRBS patterns, SONET/SDH frame patterns, and test patterns for FDDI LAN applications

Figure 2610 Error detection using an exclusive-OR gate simply involves comparing bit by bit the received pattern with the reference pattern When a difference is present, the exclusive-OR gate gives an output

bit Errored bit identification helps the user to focus on the portion of pattern that creates problems and then to investigate the causes Counting bits from the start of the pattern as a reference point, the instrument locates the position of an errored bit and identifies it On successive repeats of the pattern it calculates the bit BER, which, if the cause is systematic, will be far higher than the average BER for the pattern Of course, if the error is purely random, then on average the bit BER will be similar to the overall average This capability, in conjunction with a digital sampling oscilloscope, is useful to an engineer designing equipment and trying to locate the often complex sources of errors For example, reflections in transmission lines often give rise to pulse degradation that is many bits delayed from the launch pulse By monitoring a frequently errored bit, the engineer can adjust the word pattern to explore the effects of ISI and reflections The reference pattern for error detection could be supplied locally from the pattern generator, but normally a separate reference pattern generator is provided in the error detector so that the transmit and receive portions of the test equipment can be separated an important requirement for end-to-end testing of telecommunications links

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Synchronization This raises the question of synchronization of the two patterns to be compared before error detection can commence In order to synchronize rapidly yet remain synchronized at high error rates or during large error bursts, it s necessary to establish a sync criterion BER that has variable gate times over which a test for synchronicity is made The sync criterion may be expressed as

sync gain = sync loss x/n = X/N where x and X = error counts n and N = total bit counts x << X n << N

(262a) (262b)

(Note: To avoid oscillation, it is normal to make the sync loss BER greater than the sync gain BER, while the gate time for sync gain is much less than for sync loss The longer period for sync loss ensures that the error detector is not thrown out of lock by a burst of errors For example, one test set has a sync loss criterion of >20,000 errors in 500,000 bits and a sync gain criterion of <4 errors in 100 bits) The normal method of achieving synchronization is to open the feedback loop in the reference pattern shift register and feed the input data signal into the register until it is full, close the feedback loop, and test for sync (Figure 2611) Clearly, two PRBS patterns out of sync have a BER of approximately 05, so the sync criterion must be lower than this Some error detectors allow the user to set the sync gain/loss

Figure 2611 To obtain pattern synchronization in a closed-loop error detector, the feedback loop on the reference pattern generator is opened temporarily, and a sample of the input bit pattern is fed into the shift register The loop is then closed, and a synchronization check is made by checking the output of the error detector A BER of approximately 05 indicates a loss of synchronization In this case, the process is repeated until synchronization is obtained Some test sets allow the criteria for sync gain and loss to be adjusted for a particular application

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