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2655 Clock rates
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For telecommunications applications, a few standard bit rates are all that is required Table 269 shows the most common rates and the required clock accuracy to meet the interface specifications
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Bit Error Rate Measurements and Error Performance Analysis Bit Error Rate Measurements
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TABLE 269 Clock Tolerance at
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Hierarchial Interfaces Clock Rate PDH 64 kbps 1544 Mbps (DS1) 2048 Mbps (E1) 8448 Mbps 34368 Mbps 44736 Mbps (DS3) 139264 Mbps SONET/SDH 5184 Mbps (STS-1) 15552 Mbps (STS-3, STM-1) 62208 Mbps (STS-12, STM-3) Tolerance 100 ppm 50 ppm 50 ppm 30 ppm 20 ppm 20 ppm 15 ppm <46 ppm* <46 ppm* <46 ppm*
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* Normally synchronized to the system clock to avoid excessive pointer movements
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For general applications, a synthesized clock source is more useful Sometimes this is a built-in capability; sometimes an external synthesizer is required, in which case a clock input is specified on the pattern generator The clock input should be compatible with the synthesizer output, which probably will be a sine wave For best jitter performance, the synthesizer should have low single-sideband phase noise, eg, 140 dBc/Hz
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2656 Error measurements
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All test sets will provide the basic error measurements such as error count and bit error ratio in a timed gating period If the test set operates only with PRBS or word patterns, then the errors detected will be simply logic errors from bit-by-bit comparison with the reference pattern generator If the tester has framed data capability, then errors also can be detected in frame words and in coding The range or error types might include the following:
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Out-of-service measurements Logic errors or bit errors (binary reference pattern comparison) In-service measurements Frame errors CRC-4 or CRC-6 code errors Remote end block errors (REBE) or far end block errors (FEBE) Parity errors Interface code errors or bipolar violations
As mentioned in section 2641, an error detector capable of operating with framed signals can derive one or more of the in-service measurements just listed These might or might not be important in your application, but measurements on operational telecommunications equipment increasingly require this facility Frame
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Bit Error Rate Measurements and Error Performance Analysis 624 Network Test Instrumentation
errors are detected by checking for any errored bits in the periodic frame alignment signal (FAS) Cyclic redundancy checksum (CRC-4 and CRC-6) is calculated on blocks of live data, and the remainder is transmitted as part of the frame structure At the receiving end, the error detector decodes these data and compares them with the locally calculated CRC remainder A discrepancy indicates one or more errors in the data block This powerful method of in-service error checking is becoming universally accepted internationally (CRC-4) and in North America (CRC-6) In North American DS3 systems and in the new generation of SONET equipment, a similar in-service check is provided by parity error checks on the stat bits in the frame A further enhancement is REBE or FEBE, whereby block error information detected by CRC or parity is sent back to the transmitting end by means of the frame structure Lastly, the interface code itself can be checked for errors Review the specification of the error detector for how many error types are available and for compliance with the international or North American standards Error analysis normally will be included based on ITU-T Recommendation G821, described in section 2633 This is based on the 1-second error-free interval Some test sets also provide finer resolution of the interval down to 1 ms, which can be useful in research work and field trials Some test sets incorporate G821 Annex D additions and possibly analysis according to the new ITU-T Recommendation M2100 and G826 for maintenance of telecommunications links Lastly, look at the data-logging capabilities provided Long-term tests result in a lot of data, so a means for storing them and displaying them graphically can be a valuable facility
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