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Frequency Synthesizer Design
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45 degrees, which is a good compromise between loop stability and loop response T3/T1 percent Normally chosen to be 45 percent T3/T1 is the ratio, expressed as a percentage, of the poles of the loop filter The higher this value (the closer to 100 percent) the more the reference spurs will be attenuated; but peaking will begin to occur within the filter s passband, and R3 will increase in value, adding excessive thermal noise MHz The frequency of the reference oscillator before the R FREF divider Must be a multiple of FCOM 10 MHz is a popular value, as applicable After filling out these required parameters, design the complete frequency synthesizer by performing the following calculations (or simply use the included National Semiconductor EasyPLL software): 1 N 2
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FOUT FCOMP 2 FC 1 cos tan T3/T1 1 100 T1
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6 C1 7 C2 8 C3 9 R2 10 R3
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T1 T2 C1 C1 10 T2 C2 T3
K KVCO 2 C N T2 T1 1
T )(1
C3 If a broadband VCO is required in the synthesizer design, then more DC tuning voltage will also be needed, since very wideband VCOs may demand up to 20 or more tuning volts; but a typical narrowband PLL chip may be able to supply only 5 V or less This increase in the necessary DC tuning voltage for a
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Frequency Synthesizer Design
Frequency Synthesizer Design
wideband VCO can be accomplished by employing a separate op-amp within the PLL filter as shown in Fig 56 The VCO gain would then be: VCOGAIN KVCO A v
where Av voltage gain of the op-amp and KVCO gain of the VCO in MHz/V (The entire PLL design will still be the same as in steps 1 through 10 above, but now simply substitute KVCO for VCOGAIN) Another popular technique is to place a low-noise, high-supply-voltage opamp at the DC tuning input of the VCO with the loop filter s output placed into the input of the op-amp and use the VCOGAIN formula above to calculate the new gain of the VCO The result of the VCOGAIN calculation will be used as the new KVCO in the above PLL formulas This completes the design of the most important part of a PLL synthesizer, the loop filter The following will wrap up the total frequency synthesizer design by employing one of the most popular family of PLL chips in use today: the National LMX23XX (Fig 57) The complete National PLL chip s input and output pins are described in detail below for the widely used LMX2306 (which functions up to 550 MHz), the LMX2316 (functions up to 12 GHz), and the LMX2326 (functions up to 28 GHz): 1 Flo is an output pin that permits a parallel resistor to be attached between C2 and R2 of the PLL s loop filter This will allow the PLL to obtain both a fast lock time and good phase noise specs by modifying the loop bandwidth on the fly After the channel change occurs, loop bandwidth reverts back to normal 2 CPo is the output of the charge pump to which the loop filter is attached
Figure 56 Circuit to increase the tuning voltage for wideband VCOs
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Frequency Synthesizer Design
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3, 4 GND at Pins 3 and 4 are for the charge pump and for the analog circuits respectively Both can be short-circuited together and attached as directly as possible to system ground 5 fIN should be AC-shorted to ground through a 100-pF capacitor 6 fIN accepts the signal from the VCO s output through a series 20- to 200ohm resistor The series resistor, whose value depends on the VCO s output power, will lower the power into the preselector, allowing most of this energy to be delivered to the load 7 Vcc1 pin is the heavily bypassed DC analog power supply voltage input The input voltage for this particular chip may be anywhere between 23 and 55 V; but must equal pin 15 s Vcc2 voltage 8 OSCIN is the reference oscillator input for a CMOS 100-kilohm output resistance clock oscillator A clean crystal clock input is vital for a lowphase-noise PLL output 9 GND is digital ground It should reach system ground by as direct a route as possible 10 CE is the chip enable pin when power is down for power-saving operation It can be tied to VCC if this feature is not required 11 CLK is an input that accepts a CMOS clock signal from the channel select microcontroller for clocking data into pin 12 12 DATA input accepts data from the microcontroller for the R counter, the N counter, and the function latch (which controls phase detector polarity, fast-lock modes, Fo/LD, counter reset, CP tristate, test modes, etc), with the last two bits (control bits) informing the PLL as to whether the data should be sent to the R counter (0, 0), the N counter (1, 0), or the function latch (0,1) on command of pin 13, LE 13 LE (load enable) pin controls when the PLL s registers will send data to the R, N, or function latches, depending on the control bits 14 Fo/LD is an output pin that can typically be used as a lock detect (LD) output pin into a microprocessor, or into some out-of-lock alarm A HIGH will be output when the PLL is in lock (on advanced PLL chips, such as with the National line, a trace may be taken from the lock detect (LD) pin back to the microprocessor The pin, if digital lock detect is chosen by programming the proper PLL register, will output a HIGH as long as the VCO output frequency is locked This HIGH or LOW signal can then be exploited by the microprocessor to indicate an unlocked condition by an LED warning on a display, or as an automatic shutdown of a runaway transmitter) 15 VCC2 is the digital power supply voltage input pin, and should be tied to pin 7, which is the analog power supply input 16 Vp is the power supply for the charge pump circuit, and must be greater than VCC (The DC control voltage into the VCO will always be a few
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