To Design in Software

Making Code 128 Code Set A in Software To Design

1 Choose a proper high frequency transistor with an fT that is much higher than the oscillation frequency (5 to 10 times is a good choice) 2 Bias the active device as Class A by the following procedure: a Choose the supply voltage Select the Q-point for the transistor that is consistent with the available S-parameter file for IC and VC Example: IC = 5 mA; VC = 3V; VCC = 5 V Find transistor s typical beta, such as b = 80 b Calculate RB = VC 07 IC

3 Calculate the values for the LC resonator and other components by: L1 = C3 = 190 2 f C1 = 1 24 f C2 = 1 24 f

1 300 f

RE = < 15 (as required to force the oscillator s open-loop input/output ports closer to the same real impedance value) 4 Check ZIN and ZOUT for equality when performing the preliminary open-loop S-parameter analysis Both Rf and RE can then be tuned, if needed, until both the oscillator s input and output impedances are closer to the same real value, preferably 50 5 CCOUP 50 to 200 (XC) for a 50- load Find the necessary value of CCOUP by simulating the oscillator into a 50- load, and then use the lowest CCOUP reactance value that will still allow the oscillator to maintain a decent gain margin (> 3) (If a high input impedance buffer amplifier follows CCOUP, then CCOUP = CC) 6 Simulate and optimize as explained in Sec 42

the oscillator However, if the L1 to C3 ratio is too high, the frequency tuning of the oscillator via C3 can become excessively sensitive

A Quick Example Design a Discrete LC BJT Oscillator (Fig 420) Goal: Create a discrete LC oscillator for RF frequencies The specifications and parameters for the circuit are: POUT = +1 dBm (The DC bias can be raised to higher levels for more POUT) VCC = 5 V fr = 400 MHz VCE = 2 V IC = 10 mA Transistor = NXP BFG-425W Solution: 1 RFC = 200 nH 2 RC = 296 3 RB = 104 k 4 Rf = 500 (tuned to 260 ) 5 CC = 398 pF 6 CCOUP = 796 pF (50 at 400 MHz) 7 C1, C2 = 331 pF 8 C3 = 265 pF (optimized to 2374 pF) 9 L1 = 756 nH 10 RE = 10 (for gain reduction, improved impedance match, and a closer 180 phase shift) 11 Tune for optimal response, as required

LC (Rhea Type) MMIC Oscillator Design for up to 900 MHz (Fig 421)

1 Calculate a T network resonator as shown in the Chap 3, or use the online Java matching calculator by John Wetherell, called Impedance Matching Network Designer (available at multiple Web sites) Select a Q of greater than 13, an input/output impedance of 50 , and the desired oscillation frequency A high loaded resonator Q is critical for proper operation of the oscillator and for low phase noise, so select a high-Q inductor and capacitor, as well as making sure that the T network has a high L/C ratio (which will be guaranteed by choosing a high loaded-Q for the above calculations) 2 A VCC should be selected for the MMIC that will permit at least 2 V (preferably 4 V) to be dropped across RBIAS for proper stability: RBIAS = VCC VMMIC I MMIC

where VMMIC = DC voltage required at the MMIC s power pin, V, IMMIC = DC current required into the MMIC s power pin, A

Port_1 50

CBLOCK 398 pF Port_2 50