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f out
10 MHz f osc FREQUENCY f REF PHASE DIVIDER CRYSTAL 10 MHz 1 MHz COMPARE ( f 10) OSC
FULL REFERENCE FREQUENCY FROM CRYSTAL SOURCE DIVIDED REFERENCE FREQUENCY OF CRYSTAL SOURCE
PLL LOOP FILTER (DC FILTER)
ERROR VOLTAGE FILTERED TO DC
FREQUENCY SYNTHESIS OUT 100 MHz HIGH STABLE OUTPUT FREQUENCY FROM AN LC OSCILLATOR
f out
ERROR VOLTAGE (OR CURRENT) GENERATED WHEN VCO IS OFF FREQUENCY
FIGURE 51
The phase-locked loop frequency synthesizer
the N- and R-dividers to see if they are of the same phase, it will produce a rectified DC correction voltage, Verror, at its output port, which is then placed into the PLL loop filter if these two fCOM and fREF frequencies differ This lowpass filter almost completely eliminates any AC variations and noise products emanating from the PFD s output port, and places the now nearly pure DC correction voltage (VCNTRL) directly into the VCO s frequency control input The VCO immediately generates a variable and controllable output frequency that is as stable as the reference oscillator s fosc
Loop Filter
The all-important PLL loop filter is required to filter powerful phase comparator constituents at the comparison frequency of fCOM, and its harmonics, since if these responses actually reached through to the VCO stage they would adversely modify VCO stability A standard three-pole loop filter (Fig 52), which will form a fourth-order loop (with the other pole supplied by the PLL), is comprised of R2 and C2, which are the
PLL INTEGRATED CIRCUIT
PASSIVE LOOP FILTER
COUNTER 1/R DIVIDER
R3 C1 C2 R2 C3
fout
N DIVIDER
FIGURE 52
A standard loop lter for a PLL
Frequency Synthesis Design
main AC-to-DC filtering elements: C1, which aides in AC attenuation, and R3 and C3, used for additional lowpass filtering to further reduce PLL spur amplitudes The loop filter s capacitors should not be of the ceramic type due to ceramic s natural piezoelectric noise generation capabilities, with low leakage film capacitors being the preferred type Also, the loop s resistors should not be the noisy carbon composition types, but only of the thin or thick film variety
Voltage Controlled Oscillator
The varactor diode s bias within the voltage controlled oscillator (VCO) circuit is controlled by the PLL s DC voltage VCNTRL, which immediately forces the VCO back on frequency if it has drifted off This action permits a varactor LC oscillator to be adjustable over many discrete frequencies, and with the full stability of a crystal oscillator
N-Divider
The N-divider is made of three separate counters, the prescaler, the A counter, and the B counter By far the most common N-divider/prescaler is the dual modulus type, which supplies two separate prescaler divide rates, permitting the synthesizer to function at rapid tuning speeds and high frequencies, and with a relatively fine tuning resolution It accomplishes this by internally dividing the input frequency by more than one divide ratio, such as 8/9 or 16/17 Consequently, instead of only being able to reach a specific frequency by dividing by, let s say, 8 a certain number of times, the PLL s 8/9 prescaler can now also divide by not only 8, but also by 9 for a set number of times This gives us for more frequencies that we can synthesize, while also maintaining a decent frequency step resolution Therefore, prescalers (Fig 53) take the high frequency of the VCO and divide it down to a more manageable lower frequency in the N-divider section: The VCO frequency is fed into this prescaler, which divides the frequency down to P + 1, in which P stands for the size of the prescaler At each of these P + 1 cycles, A + B counters decrement by 1 This creates a count of A(P + 1) and (B A)P, which makes N = A(P + 1) + (B A)P, or P(B + A) N is not permitted to be less than P(P 1), and if N is less than this P(P 1), then B A, with: B= N P and A = N (B P) and N= fout fCOM
CONTROL WORDS
"N" PROGRAMMABLE COUNTER
f in HIGH f
PRESCALER 32/33
SWALLOW "A" COUNTER
PROGRAMMING "B" COUNTER
f in LOW f
SWALLOW CONTROL
FIGURE 53
A block diagram of a prescaler
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The final outcome of using these dual-modulus prescalers in N-divider PLLs is that it becomes possible to control the division ratio into the phase comparator in steps of 1(N), as opposed to the huge steps of 32 or 33 in a fixed modulus 32 or 33 prescaler This N value must always be an integer, with the largest N value being determined by the size of the B counter, since N = P(B + A) Dual-modulus prescalers will, however, have certain illegal divide ratios, in which specific frequencies cannot be generated If a particular N value results in a B register that is smaller than the A register, this will not be allowed; since B must be greater than or equal to A for a legal divide ratio In other words, not all N values are allowed with a dual-modulus prescaler equipped PLL The tradeoff between having certain frequencies that are impossible to generate is that we can obtain better frequency resolution at the PLL s output than would normally be possible However, if certain frequencies must be generated by the PLL dual-modulus prescaler (since N must equal (P + 1) (A + P) (B A) to be a legal divide ratio), then a legal divide ratio check should be performed by using National s Easy PLL or National s Code Loader program
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