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Phase-Frequency Detectors
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The PLL s phase-frequency detector detects a change in phase between fCOM and fREF It does this by lining up the rising edges of fCOM and fREF, and then outputs control signals to the charge pump to tell it to sink or source current in or out of the lowpass loop filter to keep the PLL locked The charge pump outputs a single amplitude, but changeable duty cycle, current pulse which the loop filter converts into a DC output voltage This filtering action removes most of the charge pump s glitches and overshooting, instructing the VCO to move slightly higher or slightly lower in frequency if it has drifted or if the operator/command-signal desires a rapid change in frequency When the fCOM and fREF inputs to the PFD are perfectly aligned in both frequency and phase, then the loop is deemed fully locked This locked condition is very temporary due to the extremely poor frequency stability of a VCO During the short period of perfect lock when fCOM and fREF are in perfect frequency and phase alignment, the charge pump will tri-state with a high-impedance output and with narrow (approximately 30 ns wide) positive and negative charge-pump current pulses at a 50-50 duty cycle The outputting of pulses even when in perfect lock is done to prevent dead-band behavior The PLL dead-band is a condition in which the phase-frequency detector would have no control of the loop when the PLL was very close to, or is actually in, lock In other words, when there is an almost 0 phase difference between fCOM and fREF (This is so, jitter is not created with the excessive PLL loop hysteresis) And even though the PFD is still outputting current pulses when fCOM and fREF are in perfect in-phase alignment, the charge pump itself will neither charge up nor charge down the loop filter s capacitors, since these charge-pump pulses are comprised of evenly spaced, 50-50 duty cycle, very narrow Iup and Idwn pulses Unlike many of the old PLL detectors, all modern PLL chips use PFDs which will force a lock, even when the PLL itself is drastically out of lock The PFD does this by first comparing, then finding the same fCOM and fREF frequency, and only after it completes this wide frequency lock function does it then force an almost perfect fine tune phase lock for the synthesizer circuit
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Most modern PLL chips are of the charge-pump type (Fig 54) A PLL with a charge pump permits the use of a passive filter, which is cheaper and adds little extra noise, unlike an active op-amp-based loop filter
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A charge pump PLL chip
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The built-in charge pump outputs a current of steady amplitude, but with a changeable duty cycle and polarity, into the PLL s loop filter The charge pump s duty cycle changes depending on how far out-of-lock the VCO is: wider pulses mean that the VCO is farther out of lock than narrow pulses, and that the VCO requires a higher VCNTRL level The filter then converts this charge-pump current output into a DC control voltage for the VCO s input control port, VCNTRL All PLL charge pumps can be considered as being comprised of two well-matched current sources that are switched fully on or fully off by the PFD The charge pump itself can do only one of three things: it can source current, sink current, or go into a high-impedance (tri-state) mode A charge pump s output is connected to the simple loop filter of Fig 55 to demonstrate charge-pump/loop-filter action: As soon as the PFD senses that fREF and fCOM are not perfectly equal, a phase error is detected and the PFD sends a voltage command to the charge-pump circuit to turn on Iup, which begins to charge C1 through R1 This causes VCNTRL to ramp up to a value of I R1 Iup is then ordered by the PFD to shut off at the same time that Idwn is ordered on, which draws the current back out of C1, through R1, and sinks it through Idwn, causing the VCO control voltage VCNTRL to drop to a lower value, and changing the fout value from the VCO s output port (We could actually calculate this VCNTRL value by taking the average DC current that is pumped out of the charge pump and multiplying it by the loop filter s impedance) Low-voltage charge pumps, which are used with a typical passive loop filter, depend largely on the charge pump s voltage supply (and the charge pump s current setting) for the best lock time, since the charge-pump gain will increase in a linear manner with its voltage supply amplitude Thus, the higher the charge pump s supply voltage, the faster the charge-pump output forces the loop-filter voltage to reach a steady-state value into the VCNTRL port of the VCO, and therefore the faster the PLL lock time This effect is due to the loop filter itself (Fig 56), since as the charge pump begins to pulse current into the filter to force the VCO s voltage to some specific amplitude, these pulses begin to charge,
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