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Print Code 128 Code Set C in Software C = 2 fc 1 cos( ) tan( ) 3 T1 = T3 / T1 C + 1 100

2 C = 2 fc 1 cos( ) tan( ) 3 T1 = T3 / T1 C + 1 100
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Frequency Synthesis Design
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T3 / T1 T1 100 1 C 2 (T1 + T3 ) T1 K K VCO T2 C 2 N 1 + C 2 T2 2 2 (1 + C T12 )(1 + C 2 T3 2 )
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4 T3 = 5 T2 =
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T 7 C2 = C1 2 1 T1 8 C = C1 3 10 9 R2 = T2 C2
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T3 10 R3 = C 3 If a wide tuning VCO is required in a broadband synthesizer design, then more DC tuning voltage for the VCO will also be needed, since very wideband oscillators may demand up to 20 or more tuning volts but a typical narrowband PLL chip may only be able to supply 5 V or less This increase in the necessary DC tuning voltage for a wideband VCO can be accomplished by employing a separate op-amp within the PLL filter as shown in Fig 59 The VCO gain would then be: VCOGAIN = KVCOAv where Av = voltage gain of the op-amp, KVCO = gain of the VCO, MHz/V
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R5 R2 R4
OP-AMP CIRCUIT
FIGURE 59 Active loop lter used to increase the tuning voltage for high V TUNE, wideband VCOs
Five
NATIONAL LMX 2306/16/26 FLo CPo GND GND fin fin VCC1 OSCIN
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
Vp VCC2 Fo/LD LE DATA CLK CE GND
FIGURE 510
A popular PLL chip, the National LMX23XX series
The entire PLL design will still be the same as in steps 1 through 10 above, but now simply substitute KVCO for VCOGAIN Another similar wideband tuning technique is to place a low-noise highsupply voltage op-amp directly at the DC tuning input of the VCO, with the loop filter s output placed into the input of the op-amp, and use the VCOGAIN formula above to calculate the new gain of the VCO The result of the VCOGAIN calculation will then be used as the new KVCO in the above PLL formulas C The above completes the design of the most important part of any PLL synthesizer, the loop filter The following will wrap up the total frequency synthesizer design by employing a National LMX23XX PLL chip (Fig 510) The complete National PLL chip s input and output pins are described in detail below for the 16 pin TSSOP package of the popular LMX2306 (which functions up to 550 MHz), the LMX2316 (12 GHz), and the LMX2326 (28 GHz): 1 Flo is an output pin that permits a parallel resistor to be attached between C2 and R2 of the PLL s loop filter This will allow the PLL to obtain both a fast lock time and good phase noise specs by modifying the loop bandwidth on the fly After the channel change occurs, loop bandwidth reverts back to normal 2 CPo is the output of the charge pump to which the loop filter is attached 3 Pin 3 GND is for the charge pump, and can be shorted to Pin 4 and attached as directly as possible to system ground 4 Pin 4 GND is for the analog circuits, and can be shorted to Pin 3 and attached as directly as possible to system ground 5 fin should be AC shorted to ground through a 100-pF capacitor 6 +fin accepts the signal from the VCO s output through a series 20 to 200- resistor This series resistor, whose value is dependent on the VCO s output power, will lower the power into the preselector, allowing most of this energy to be delivered to the load
Frequency Synthesis Design
7 VCC1 pin is the heavily bypassed DC analog power supply voltage input The input voltage for this particular chip may be anywhere between 23 and 55 V, but must equal pin 15 s VCC2 voltage 8 OSCIN is the reference oscillator input for a CMOS 100 k output resistance clock oscillator A clean crystal clock input is vital for a low-phase-noise PLL output 9 GND is digital ground Should reach system ground by as direct a route as possible 10 CE is the chip enable pin for power down for power saving operation Can be tied to VCC if this feature is not required 11 CLK is an input that accepts a CMOS clock signal from the channel select microcontroller for clocking data into pin 12 12 DATA input accepts data from the microcontroller for the R-divider, the N-divider, and the Function Latch (which controls phase detector polarity, FastLock modes, Fo/LD, counter reset, CP tri-state, test modes, and so on), with the last two bits (control bits) informing the PLL as to whether the data should be sent to the R-divider (0,0), the N-divider (1,0), or the Function Latch (0,1) on command of pin 13, LE 13 LE (load enable) pin controls when the PLL s registers will send data to the R-divider, N-divider, or Functions Latches, depending on the control bits 14 Fo /LD is an output pin that can typically be used as a lock detect (LD) output pin into a microprocessor, or into some out-of-lock alarm A High will be output when the PLL is in lock (On advanced PLL chips, such as with the National line, a trace may be taken from the LD pin back to the microprocessor The pin, if digital lock detect is chosen by programming the proper PLL register, will output a high as long as the VCO output frequency is locked This high or low signal can then be exploited by the microprocessor to indicate an unlocked condition by an LED warning on a display, or as an automatic shutdown of a run-a-way transmitter) 15 VCC2 is the digital power supply voltage input pin, and should be tied to pin 7, which is the analog power supply input 16 Vp is the power supply for the charge-pump circuit, and must be greater than VCC (The DC control voltage into the VCO will always be a few tenths of a volt less than Vp, so Vp must have the proper amplitude to fully drive the VCO s DC control input, VCNTRL) D After completing the filter s design calculations for the frequency synthesizer, the following final PLL design checks must be performed to confirm that the PLL will function as desired: 1 The loop bandwidth, fc, should be at least
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