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Frequency Synthesis Design in Software
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Printing 2D Barcode In Visual Basic .NET Using Barcode maker for .NET Control to generate, create Matrix 2D Barcode image in VS .NET applications. Print Code 128A In Java Using Barcode creation for Eclipse BIRT Control to generate, create Code 128 image in BIRT applications. 10 101 Frequency (KHz) 100 90 80 70 60 50 40 30 20 10 0 10 20 30 40 50 60 70 80 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 TOTAL NOISE
VCO NOISE R3 NOISE PLL NOISE
R2 NOISE
TCXO NOISE
10 1 100 Frequency (KHz) 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 Phase deg
Gain (dB) 2575 2570 2565 2560 2555 2550 2545 2540 2535 2530 2525 2520 2515 2510 2505 2500 2495 2490 2485 2480 2475 2470 2465 2460 2455 2450 2445 2440 2435 2430 2425 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 Frequency (MHz) Time (uS) FIGURE 512 An active loop- lter PLL design example: (a) loop gain/phase response; (b) phase noise; (c) PLL lock time Five
Loop bandwidth = 2 kHz Charge-pump gain = 1 mA Phase margin = 45 T3/T1 ratio = 100% (A high T3/T1 above 100% is commonly used in active filter designs for the best loop filtering of op-amp noise and PLL spurs) PLL IC = National LMX2326 VCO = RFMD VCO790-2300T (1885-MHz/V, 68-pF input capacitance) Solution: 1 Using the calculated values as presented, or by quickly employing the online version of National s EasyPLL, enter the above desired PLL specifications 2 Run the software, which should results in the following loop-filter values: a C1 = 22 nF b C2 = 220 nF c C3 = 10 nF d R2 = 820 e R3 = 15 k f RA = 18 k g RB = 12 k 3 Analyze the design The results should be: a Phase noise PN@009 kHz = 6596 dBc/Hz PN@1000 kHz = 7516 dBc/Hz b Filter (Bode) Loop BW = 193 kHz Phase margin = 4319 c Lock time Lock time = 18324 s (Which, in this example, is until the loop settles to within 500 Hz of the desired frequency of 25 GHz after being ordered to travel up from 24 GHz) Or, if a fractional-N passive loop PLL synthesizer is called for, such as when a tight channel spacing is required, use the Quick Example below A Quick Example Design a Fractional-N Passive Loop PLL Synthesizer (Fig 513) Goal: Using the enclosed ADIsimPLL software, create a fractional-N phase-locked loop synthesizer with an RC loop filter The specifications and parameters for the circuit are: fr = 24 to 25 GHz (center frequency = 245 GHz) VCC = 5 V fREF = 10 MHz fCOM = 100 kHz Channel spacing = 100 kHz Filter = third order Loop bandwidth = 2 kHz Charge-pump gain = 1 mA (938 uA) Phase margin = 45 Frequency Synthesis Design
RFIN fREF VCC Fout /RFIN
R2 C1 R1 C2 C3
fout
RSET
RSET
FIGURE 513 A passive loop- lter fractional-N PLL design example (ADIsimPLL): (a) loop gain/phase response; (b) phase noise; (c) PLL lock time PLL IC = Analog Device s ADF4154 VCO = RFMD VCO790-2300T (1885-MHz/V, 68-pF input capacitance, PN = 90 dBc/Hz @ 10 kHz, PN = 112 dBc/Hz @100 kHz) Solution: 1 Using the calculated values as presented in this book, or by quickly employing the enclosed ADIsimPLL, enter the above desired PLL specifications Five
2 Run the software, which should result in the following loop-filter values: a C1 = 382 nF b C2 = 52 uF c C3 = 174 nF d R1 = 429 e R2 = 876 3 Analyze the design The results should be: a Phase noise (total) PN@100 Hz = 7866 dBc/Hz PN@1000 kHz = 891 dBc/Hz b Filter (Bode) Loop BW = 200 kHz Phase margin = 4500 c Lock time Lock time = 141 mS (Which, in this example, is until the loop settles to within 1000 Hz of the desired frequency of 25 GHz after being ordered to travel up from 24 GHz)
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