Figure 1017 Hardwired design of the divisor in CRC
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Leftmost bit of the part of dividend involved in XOR operation
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Note that if the leftmost bit of the part of dividend to be used in this step is 1, the divisor bits (d2d 1do) are all; if the leftmost bit is 0, the divisor bits arc 000 The design provides the right choice based on the leftmost bit
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In our paper-and-pencil division process in Figure 1015, we show the augmented dataword as fixed in position with the divisor bits shifting to the right, 1 bit in each step The divisor bits are aligned with the appropriate part of the augmented dataword Now that our divisor is fixed, we need instead to shift the bits of the augmented dataword to the left (opposite direction) to align the divisor bits with the appropriate part There is no need to store the augmented dataword bits
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In our previous example, the remainder is 3 bits (n - k bits in general) in length We can use three registers (single-bit storage devices) to hold these bits To find the final remainder of the division, we need to modify our division process The following is the step-by-step process that can be used to simulate the division process in hardware (or even in software) 1 We assume that the remainder is originally all Os (000 in our example)
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2 At each time click (arrival of 1 bit from an augmented dataword), we repeat the following two actions: a We use the leftmost bit to make a decision about the divisor (011 or 000) b The other 2 bits of the remainder and the next bit from the augmented dataword (total of 3 bits) are XORed with the 3-bit divisor to create the next remainder Figure 1018 shows this simulator, but note that this is not the final design; there will be more improvements
Figure 1018 Simulation of division in CRC encoder
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At each clock tick, shown as different times, one of the bits from the augmented dataword is used in the XOR process If we look carefully at the design, we have seven steps here, while in the paper-and-pencil method we had only four steps The first three steps have been added here to make each step equal and to make the design for each step the same Steps 1, 2, and 3 push the first 3 bits to the remainder registers; steps 4, 5, 6, and 7 match the paper-and-pencil design Note that the values in the remainder register in steps 4 to 7 exactly match the values in the paper-and-pencil design The final remainder is also the same The above design is for demonstration purposes only It needs simplification to be practical First, we do not need to keep the intermediate values of the remainder bits; we need only the final bits We therefore need only 3 registers instead of 24 After the XOR operations, we do not need the bit values of the previous remainder Also, we do
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not need 21 XOR devices; two are enough because the output of an XOR operation in which one of the bits is 0 is simply the value of the other bit This other bit can be used as the output With these two modifications, the design becomes tremendously simpler and less expensive, as shown in Figure 1019
Figure 1019 The CRC encoder design using shift registers
We need, however, to make the registers shift registers A I-bit shift register holds a bit for a duration of one clock time At a time click, the shift register accepts the bit at its input port, stores the new bit, and displays it on the output port The content and the output remain the same until the next input arrives When we connect several I-bit shift registers together, it looks as if the contents of the register are shifting