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where s(Th1 ) denotes the seek component of the performance parameter Similarly, we can evaluate the total time spent for the rotational delay constituent, for the data transfer constituent, and for the processing constituent, so that for any constituent 0qh2 =
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Here h2(Th1 ) denotes the constituent h2 of the operation Th1 The values qh2 give the demand on the system for the constituent due to the load imposed in a given period We have not evaluated the processor component c throughout, but it is useful to carry it here in symbolic form to verify the assumptions made in Sec 2-3-2 relative to bu ering and the bulk transfer rate t If the nal system requires multiple components to satisfy the load, the demand on c grows proportionally, so that faster or multiple processors will be needed In Sec 5-4-4 we investigate opportunities of parallel operations of various system components, in order to determine the quantity of basic operations that a computer system can deliver
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The constituents of production demand q will have to be distributed onto the components of the system in order to obtain estimates of the utilization u for the various types of components We refer to Fig 5-8 to obtain the conditions for the assignment of q, appropriate for the storagesystem architecture We will assume now that we have a class 5 or 6 machine These machines provide the greatest capability for overlap of constituents The average utilization for a disk includes all but the computation time so that (1 + fus)qs + qr + qbtt 5-7 Q where fus denotes the fraction of time in terms of s, < (shown in Fig 5-8), needed <1 to get the seek mechanism started We will discuss this term in the next paragraph The controller and channel can be evaluated similarly: the controller is free while the disk unit is seeking; the channel is active only during command and data transfer fus qs + qr + qbtt ucontrollers = Q 5-8 fus qs + qbtt uchannels = Q If s the controller can control multiple disks simultaneously without creating a r, bottleneck If s + r btt, the channel can control multiple controllers with active disks simultaneously without creating a bottleneck The term f us will take into account the control tra c when s + r btt For the processors udisks = qc + fus qs computational load 5-9 Q If we do not have accurate data on processor usage, we go back to our assumptions about bu ering, where we stated that we expect that c Bfr < btt (Eq 2-22), so that we can state initially qbtt bu ering constraint 5-10 uprocessors < Q uprocessors =
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E ect of Interference between Control-Information Transfer and Data Transfer The factor fus above accounts for the time it takes to trans-
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fer the control information from the processor via the channel to the disk unit Control information is required to initiate a seek, notify the processor, or perform address or key veri cation on cylinders and blocks In a class 6 machine, there is a data-independent path for such control information via each channel to the controllers The dotted line in Fig 5-7 indicates this control ow path All that is required here is the transfer of a few, (pc), pointers of size P , and if the same transfer rate applies to such control information as applies to data, then for each seek pc P pc P = btt < <btt 0 class 6 5-11 t B In the other architectural classes, control information has to share the path used fus = fus =
Sec 5-4
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