how to use barcode in rdlc report Telecommunication Integrated-Circuit Devices in Software

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TABLE 178 Telecommunication Integrated-Circuit Devices
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Radio-control transmitter-encoder Radio-control receiver-decoder Pulse-code modulator coder-decoder (PCM CODEC) Single-chip programmable signal processor Touch-tone generators Modulator-demodulator (modem)
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Internal Block Diagram Vcc (8)
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Flip Flop 1 2
Trigger
Output
Reset
Output Driver
Reset (4) Output (3)
Discharge (7)
Gnd (1)
FIGURE 1732 NE 555 timer chip
ELECTRONICS ENGINEERING
Vcc 8 R1 7 R2 3
t1 t2
2 6 C 1
t1 = 0693 x (R1 + R2) x C t2 = 0693 x R2 x C Frequency = 1446 / ((R1 + 2R2) x C)
FIGURE 1733 555 oscillator circuit
output A popular use for the 555 timer chip is to produce a timed pulse from a negative pulse input as shown in Fig 1734 the 555 is often used to debounced momentary button input as shown in Fig 1735 Other applications that can be implemented using the 555 timer chip include varying tone sirens and missing pulse detectors
DIGITAL INTEGRATED CIRCUITS
The basic circuit building block for digital ICs is the gate circuit A gate is a switching ampli er that is designed to be either on or off (By contrast, an operaVcc 8
Negative Pulse In Positive Pulse Out
R 7 6
5 Cn (01 F)
t t=RxC Note, for High values of R and C, accuracy diminishes
FIGURE 1734 555 monostable circuit
CHAPTER SEVENTEEN
Vcc 8
10 K Resistor 100 Ohms Push Button
01 uF Capacitor 100k 7 6
Positive Pulse Out
t=RxC = 10 uF x 100k = 0100 Seconds
01 F
10 uF
FIGURE 1735 555 button debounce circuit
tional ampli er is a proportional ampli er) For 5-V logic levels, the gate switches to a 0 whenever its input falls below 08 V and to a 1 whenever its input exceeds 20 V This arrangement ensures immunity to spurious noise impulses in both the 0 and the 1 state Several representative transistor-transistor-logic (TTL) gates are listed in Table 179, which references diagrams with the pinouts of the different chips The TTL part number is in the format 74xx##(#) where the xx is the logic technology speci er There are several different kinds of TTL technology for each of the chips listed in Table 179 The input parameters of these technologies are listed in Table 1710, and the output parameters are listed in Table 1711 Note that for true TTL, the threshold voltages are based on the amount of current drawn from the chip inputs Gates can be combined to form logic devices of two fundamental kinds: combinational and sequential In combinational logic, the output of a device changes whenever its input conditions change The basic gate exempli es this behavior A number of gates can be interconnected to form a ip- op circuit This is a bistable circuit that stays in a particular state, a 0 or a 1 state, until its clock input goes to a 1 At this time its output will stay in its present state or change to a new state depending on its input just prior to the clock pulse Its output will retain this information until the next time the clock goes to a 1 The ip- op has memory, because it retains its output from one clock pulse to another By connecting several ip- ops together, several sequential states can be de ned permitting the design of a sequential logic circuit Table 1712 shows three common ip- ops The truth table, sometimes called a state table, shows the speci cation for the behavior of each circuit The present output state of the ip- op is designated Q(t) The next output state is designated 1) In addition to the truth table, the Boolean algebra equations in Table Q(t 1712 are another way to describe the behavior of the circuits The JK ip- op is the most versatile of these three ip- ops because of its separate J and K inputs
(continues on page 1731)
ELECTRONICS ENGINEERING
TABLE 179 Digital Integrated-Circuit Devices
Type (74xx##) 74xx00 74xx02 74xx04 74xx06 74xx08 74xx32 74xx74 74xx83 74xx86 74xx125 74xx138 74xx139 74xx174 74xx244 74xx245 74xx373 74xx374 74xx573 74xx574
No circuits per device 4 4 6 6 4 4 2 1 4 4 1 2 6 8 8 8 8 8 8
No inputs per device 2 2 1 1 2 2 4 9 2 2 6 3 1 Common Clock and Common Clear 1 Common Enable 1 Common Enable 1 Common Clock and Common Output Enable 1 Common Clock and Common Output Enable 1 Common Clock and Common Output Enable 1 Common Clock and Common Output Enable
Function NAND NOR NOT Buffer AND OR D-Flip Flop Adder XOR Tri-Sate 3-8 Decoder 2-4 Decoder D-Flip Flop Tri-State Bi-directional Tri-State D-Flip Flop D-Flip Flop D-Flip Flop D-Flip Flop
Pinout Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748
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