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if (Rn ! Imm) PC PC Adr if (@Rn ! Imm) PC PC Adr A 0
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1011 1RRR Imm Adr
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1011 0110 / 0111 Dir Adr 1110 0100 1100 0010 Bit 1111 0100 1011 0010 Bit 1011 0011
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Bit 0 A A 0x0FF Bit Cy Bit Cy 1 1
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CHAPTER SEVENTEEN
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TABLE 1731
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Intel 8051 Microcontroller Instruction Set (Continued ) Instruction DA A Operation if ((A & 15) 0) (AC 1) A A 6 if ((A & 0x0F0) 0) (Cy 1) A A 0x060 A A 1 Rn Rn 1 Direct Direct 1 @Rn @Rn 1 A A/B B A // B Rn Rn 1 if (Rn ! 0) PC PC Adr Direct Direct 1 if (Direct ! 0) PC PC Adr A A 1 Rn Rn 1 Direct Direct 1 @Rn @Rn 1 DPTR DPTR 1 PC A DPTR if (Bit PC if (Bit PC if (C PC if (Bit PC if (C PC if (A ! PC if (A PC 1) PC Addr 1) Bit 0 PC Addr 1) PC 0) PC 0) PC 0) PC 0) PC Addr 0010 0000 Bit Address Addr 0101 0000 Address Addr 0111 0000 Address Addr 0110 0000 Address Addr 0001 0010 Adrlo AdrHi 0000 0010 Adrlo AdrHi Op Code 1101 0100
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Description Decimal Adjust for Addition
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Decrement Accumulator or Register Divide Decrement Rn and Continue if Rn 0 Decrement Direct and Continue if 0 Increment Accumulator or Register Inc DPTR Indexed Jump If Bit is Set, Jump If Bit is Set, Reset it and Jump If Carry is Set, Jump If Bit is Reset, Jump If Carry is Reset, Jump If Accumulator is NOT equal to Zero, Jump If Accumulator is equal to Zero, Jump Long Call to Subroutine (16 Bit Addr) Long Jump (16 Bit Addr)
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DEC A DEC Rn DEC Direct DEC @R0 / 1 DIV AB DJNZ Rn, Adr DJNZ Direct, Adr INC A INC Rn INC Direct INC @R0 / 1 INC DPTR JMP @(A DPTR) JB Bit, Address JBC Bit, Address JC Address JnB Bit, Address JNC Address JNZ Address JZ Address LCALL Address LJMP Address
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0001 0001 0001 0001 1000
0100 1RRR 0100 Direct 0110 / 0111 0100
1101 1RRR Adr 1101 0101 Adr 0000 0000 0000 0000 1010 0111 0100 1RRR 0100 Direct 0110 / 0111 0011 0011
0010 0000 Bit Address 0011 0000 Bit Address 0100 0000 Address
SP SP 2 @(SP) PC PC Address PC Address
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TABLE 1731 Intel 8051 Microcontroller Instruction Set (Continued )
Description Move Byte of Data
Instruction MOV A, Rn MOV A, Direct MOV A, @R0 / 1 MOV A, #Imm MOV Rn, A MOV Rn, Direct MOV Rn, #Imm MOV Direct, A MOV Direct, Rn MOV Direct, Dir2 MOV Direct, @R0 / 1 MOV Direct, #Imm MOV @R0 / 1, A MOV @R0 / 1, Direct MOV @R0 / 1, #Imm MOV DPTR, #Imm MOV C, Bit MOV Bit, C MOVC A, @A DPTR MOVC A, @(A PC) MOVX A, @R0 / 1 MOVX A, @DPTR MOVX @R0 / 1, A MOVX @ DPTR, A MUL AB NOP ORL A, Rn ORL A, Direct ORL A, @R0 / 1 ORL A, #Imm ORL Direct, A ORL Direct, #Imm CPL C, Bit CPL C, / Bit POP Direct
Operation A Rn A Direct A @(Rn) A Imm Rn A Rn Direct Rn Imm Direct A Direct Rn Direct Dir2 Direct @(Rn) Direct @Rn @Rn @Rn DPTR Cy Bit A A A A Bit Cy @(A @(A @(Rn DPTR) PC) P2) Imm A Direct Imm Imm
Op Code 1110 1RRR 1110 0101 Direct 1110 0110 / 0111 0111 0100 Immediate 1111 1RRR 1010 1RRR Direct 0111 1RRR Immediate 1111 0101 Direct 1000 1RRR Direct 1000 0101 Direct, Dir2 1000 0110 / 0111 Direct 0111 0101 Direct Imm 1111 0110 / 0111 1010 0110 / 0111 Direct 0111 0110 / 0111 Imm 1001 0000 Immlo ImmHi 1010 0010 Bit 1001 0010 Bit 1001 0011 1000 0011 1111 0010 1110 0000
Move Bit into Carry Move Carry into Bit Move from Code Space Move from External Memory
@(DPTR) P2) A A
@(Rn
1111 0010 / 0011 1111 0000 1010 0000 0100 0100 0100 0100 0100 0100 0100 0000 1RRR 0101 Direct 0110 / 0111 0100 Immediate 0010 Direct 0011 Direct, Imm
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