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Realistic Pipeline Execution Profile: (a) Actual; (b) Modeled
Equation (16) is a generalization of Equation (15) and provides a refined model for pipelined processor performance In this model, gj representsjhe fiaclLon_pf time when there are i instructions ijrithejrip^line In otherwords, g represents the fraction oftTme when the pipeline is stalled for (rV - i) penalty cycles Of course, g is the fraction of time when the pipeline is full This pipelined processor performance model is illustrated by applying it to the six-stage TYP pipeline in 2 Note that the TYP pipeline has a load penalty
M O D E R N PROCESSOR DESIGN
PROCESSOR DESIGN
of one cycle and a branch penalty of four cycles Based on the statistics from the IBM study presented in 2, the typical percentages of load and branch instructions are 2 5 % and 20%, respectively Assuming that the TYP pipeline is designed with a bias for a branch not taken, only 666% of the branch instructions, those that are actually taken, will incur the branch penalty Therefore, only 13% of the instructions (branches) will incur the four-cycle penalty and 2 5 % of the instructions (loads) will incur the one-cycle penalty The remaining instructions (62%) will incur no penalty cycles The performance of the TYP pipeline can be modeled as shown in Equation (17)
1 1 =,ioo/
J /
! / h - 1 // /*, /* 'i i I * / M
/ " /
Equation 110
^^jr* ^ - J *r _
/ f\
___-
S t y p =
013 ~ 025 (6-4) (6-1)
062 6
013 ~ 025 2 5
062 6
The resultant performance of the six-stage TYP pipeline processor is a factor of 45 over that of the sequential or nonpipelined processor Note that the TYP is a six-stage pipeline with the theoretical speedup potential of 6 The actual speedup based on our model of Equation (16) is 45, as shown in Equation (17), which can be viewed as the effective degree of pipelining of the TYP pipeline Essentially the six-stage TYP processor behaves as a perfect pipeline with 45 pipeline stages The difference between 6 and 45 reflects the difference between the potential (peak) pipeline parallelism and the achieved (actual) pipeline parallelism 1414 The Superscalar Proposal We now restate Amdahl's lawthat models the performance of a parallel processor
02 04 06 08
Vectorizability /
Easing of the Sequential Bottleneck with Instruction-Level Parallelism for Nonvectorizable C o d e Source Agerwala and Cocke, 1987
by Agerwala and Cocke [1987], plots the speedup as a function of /, the vectorizability of a program, for several values of N, the maximum parallelism of the machine Take the example of the case when N = 6 The speedup is 1 S=( l - / ) + (//6) (19)
E X A M
~ o ^ r m
( L 8 )
This model gives the performance or speedup of a parallel system over that of a nonparallel system Themachine parallelismis measured hyW, the number ofpxocessors_in the machine, and reflects the maximum number of tasks that can be simultaneously performed by the system The parameter/, however, is the vectorizability of the program which reflects the program parallelism The formulation of this model is influenced by traditional supercomputers that contain a scalar unit and a vector unit The vector unit, consisting of N processors, executes the vectorizable portion of the program by performing N tasks at a time The nonvectorizable portion of the program is then executed in the scalar unit in a sequential fashion We have already observed the oppressive tyranny of the nonvectorizable portion of the program on the overall performance that can be obtained through parallel processing The assumption that the nonvectorizable portion of the program must be exe^ cuted sequentially is overly pessimistic and not necessary If some, even low, level of parallelism can be achieved for the nonvectorizable portion of the program, the severe impact of the sequential bottleneck can be significantly moderated figure 18 illustrates this principle This figure, taken from an IBM technical report coauthored
Examining the curve for Equation (19) in figure 18, we see that the speedup is equal to 6 i f / i s 100%, that is, perfectly vectorizable A s / d r o p s off from 100%, the speedup drops off very quickly; as / b e c o m e s 0%, the speedup is one; that is, no speedup is obtained With higher values of N, this speedup drop-off rate gets significantly worse, and as/approaches 0%, all the speedups approach one, regardless of the value of N Now assume that the minimum degree of parallelism of 2 can be achieved for the nonvectorizable portion of the program The speedup now becomes S = 1 (1-/)/ 2 6
(110)
Examining the curve for Equation (110) in Figure 18, we see that it also starts at a speedup of 6 w h e n / i s 100%, but drops off more slowly than the curve for Equation (19) w h e n / i s lowered from 100% In fact this curve crosses over the curve for Equation (18) with N= 100 w h e n / i s approximately 7 5 % This means that for cases w i t h / l e s s than 75%, it is more beneficial to have a system with maximum parallelism of only 6, thatls N~=6T6ut a minimum parallelism of two for the nonvectorizable portion, than a system with maximum parallelism of N = 100 with
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