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2113 Tradeoff Clocking constraints determine the ultimate physical limit to thedepth of pipelining Aside from this limit, m a x i m u m p i p e l i n e " o ^ P l ^ e j s h ^ w h e n cost^or pipelining overhead, is considered In the hardware design of a pipelined system, me tradeoff between cost and performance must be considered A cost/performance tradeoff model for pipelined design has been proposed by Peter Kogge and is summarized here [Kogge, 1981] Models for both cost and r^rformance are proposed The cost of a nonpipelined design is denoted as G This cost can be in terms of gate count, transistor count, or silicon real estate The cost C for a *-stage pipelined design is equal to
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which means that the earliest possible arrival of X at the latches must not be sooner than the time required for the proper latching of X This inequality can be rewritten as
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where k is the number of stages in the pipeline,^, is the cost of adding each latch and61isjh^cpstjf^ Based on this cost model, the pipeline cost C is a linear function of *, the depth of the pipeline Basically, the cost of a pipeline goes up linearly with respect to the depth of the pipeline Assume that the latency in the nonpipelined system is T Then the performance of the nonpipelined design is 1/7", the computation rate The performance P of the pipelined design can be modeled as 1/(77* + S), where T is the latency of the original nonpipelined design and S is the delay due to the addition of the latch Assuming that the original latency T can be evenly divided into k stages, (77* + S) is the delay associated with each stage and is thus the clocking period of the pipeline Consequently, 1/(77* + S) is equal to the clocking rate and the throughput of the pipelined design Hence, the performance of the pipelined design is
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where T - T, is effectively the minimum clocking period T Therefore, the clocking period T m u s t ^ e j r e a t e r j h M i J ^ X ^ I ^ - a n d the maximum clocking rate cannoT exceed 1/7" Based on the foregoing analysis, two factors limit the clocking rate One is the difference between the maximum and mmunmrijroj^atioirjlelays through the l^crSamely, T - T TneotHer is the additional time required for properclocking,
Note that P is a nonlinear function of * Given these models for cost and performance, the expression for the cost/ performance ratio is <= =<^
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M O D E R N PROCESSOR DESIGN
PIPELINED PROCESSOR
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illustrate the effectiveness of pipelining without having to deal with some of the complex issues involved in instruction pipeline design These complex issues will be addressed in subsequent sections of this chapter 2121 Floating-Point Multiplication The design of a pipelined floating-point multiplier is used as the example This "vintage" board-level design is taken from a classic text by Shlomo Waser and Mike Flynn [Waser and Flynn, 1982] (Even though this design assumes 1980 technology, nonetheless it still serves as an effective vehicle to illustrate arithmetic pipelining) This design assumes a 64-bit floatingpoint format that uses the excess-128 notation for the exponent e (8 bits) and the sign-magnitude fraction notation with the hidden bit for the mantissa m (57 bits, including the hidden bit) The floating-point multiplication algorithm implemented in this design is as follows
20 30 Pipeline depth k
1 Check to see if any operand is zero If it is, the result is immediately set to zero 2 Add the two characteristics (physical bit patterns of the exponents) and correct for the excess-128 bias, that is, e + ( e - 1 2 8 )
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