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Register write I ( a ) WAW Hazard
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(b) WAR Hazard
(c) RAW Hazard
the reads and writes, then effectively total sequential execution is carried out and no hazard can occur If the stage performing the read is positioned later in the pipeline than the stage performing the write, then RAW hazards can never occur; the reason is that all the writes of leading instructions will be completed before the trailing instructions perform their reads Since pipeline hazards are caused by potential violations of program dependences, a systematic procedure for identifying all the pipeline hazards that can occur in an instruction pipeline can be formulated by considering each dependence type in turn The specific procedure employed in this chapter examines program dependences in the following order 1 Memory data dependence a Output dependence b Anti-dependence c True data dependence 2 Register data dependence a Output dependence b Anti-dependence c True data dependence 3 Control dependence We illustrate this procedure by applying it to the six-stage TYP instruction pipeline First, memory data dependences are considered A memory data dependence involves a common variable stored in memory that is accessed (either read or write) by two instructions Given a load/store architecture, memory data dependences can only occur between load/store instructions To determine whether pipeline hazards can occur due to memory data dependences, the processing of load/store instructions by the pipeline must be examined Assuming a split cache design, in the TYP pipeline, only the M E M stage can access the D-cache Hence, all accessing of memory locations by load/store instructions must and can only occur in the MEM stage; there is only one stage in the pipeline that performs reads and writes to the data memory Based on the necessary conditions presented in Figure 215 no pipeline hazards due to memory data dependences can occur in the TYP pipeline Essentially, all accesses to the data memory are performed sequentially, and the processing of all load/store instructions is done in the total sequential execution mode Therefore, for the TYP pipeline, there are no pipeline hazards due to memory data dependences Register data dependences are considered next To determine pipeline hazards that can occur due to register data dependences, all pipeline stages that can access the register file must be identified In the T Y P pipeline, all register reads occur in the RD stage and all register writes occur in the WB stage An output (WAW) dependence, denoted ib j, indicates that an instruction i and a subsequent instruction j both share the same destination register To enforce the output dependence, instruction i must write to that register first; then instruction j can write to that same register In the TYP pipeline, only the WB stage can perform writes to the
Necessary Conditions on the Pipeline Organization for the Occurrence of (a) W A W Hazards, (b) W A R Hazards, a n d (c) R A W Hazards
dependences are illustrated in the figure) In order for a WAW hazard to occur due to an output dependence i&J, there must exist at least two pipeline stages that can perform two simultaneous writes to the common variable; see Figure 215(a) If only one stage in the pipeline can write to that variable, then no hazard can occur because both writes in fact all writes to that variable will be performed by that pipeline stage according to the original sequential order specified by the program listing Figure 215(b) specifies that in order for a WAR hazard to occur, there must exist at least two stages in the pipeline, with an earlier stage x and a later stage y, such that stage jc can write to that variable and stage y can read that variable In order for the anti-dependence ibj to be violated, instruction j must perform the write, that is, reach stage x, prior to instruction i performing the read or reaching stage y If this necessary condition does not hold, it is impossible for instruction j, a trailing instruction, to perform a write prior to instruction i completing its read For example, if there exists only one pipeline stage that can perform both the read and write to that variable, then all accesses to that variable are done in the original sequential order, and hence no WAR hazard can occur In the case where the stage performing the read is earlier in the pipeline than the stage performing the write, the leading instruction i must complete its read before the trailing instruction j can possibly perform the write in a later stage in the pipeline Again, no WAR hazard can occur in such a pipeline In actuality, the necessary conditions presented in Figure 215 are also sufficient conditions and can be considered as characterizing conditions for the occurrence of WAW, WAR, and RAW pipeline hazards Figure 215(c) specifies that in order for a RAW hazard to occur due to a true data dependence iSj, there must exist two pipeline stages x and y, with x occurring earlier in the pipeline than y, such that stage x can perform a read and stage y can perform a write to the common variable With this pipeline organization, the dependence ibj can be violated if the trailing instruction j reaches stage x prior to the leading instruction i reaching stage y Arguments similar to that used for WAR hazards can be applied to show that if this necessary condition does not hold, then no RAW hazard can occur For example, if only one pipeline stage performs all
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